Write access control for double data rate write-x/datacopy0 commands

Patent metadata

Field	Value
Publication number	US-10795830-B2
Application number	US-201816041645-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Jul 20, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.

First claim

What is claimed is:

1. An apparatus comprising:
an execution engine access (EE) controller and a Dynamic Random Access Memory (DRAM) controller,
wherein the EE controller is configured to:
receive an indirect access command on a control path comprising a control path data bus and a control path address bus, the indirect access command being a command to access a DRAM device and in which at least a part of the command is received on a path other than on a data path, and
translate a target address of the indirect access command expressed on the control path data bus, and

wherein the DRAM controller is configured to:
determine whether to allow or block the indirect access command based on the translated target address,
transmit the indirect access command to a DRAM device when it is determined that the indirect access command is to be allowed, and
block the indirect access command from being transmitted to the DRAM device when it is determined that the indirect access command is to be blocked, and

wherein the DRAM device is coupled to the apparatus over a DRAM link, and
wherein the indirect access command is transmitted over the DRAM link when it is determined that the indirect access command is to be allowed.

2. The apparatus of claim 1 , wherein the DRAM link is a die-to-die link such that the apparatus and the DRAM device are incorporated in single device.

3. The apparatus of claim 1 , wherein the indirect access command is a single command that instructs the DRAM device to internally write a constant data value to a plurality of memory locations within the DRAM device.

4. The apparatus of claim 1 , wherein the indirect access command is a write-x command or a datacopy0 command.

5. The apparatus of claim 1 ,
wherein the DRAM link comprises a plurality of data (DQ) lanes, a clock (CLK) lane, a plurality of command and address (CA) lanes, and a data strobe (DS) lane, and
wherein the indirect access command transmitted on the DRAM link is such that any value on some or all of the plurality of DQ lanes is ignored by the DRAM device.

6. The apparatus of claim 1 ,
wherein the EE controller is one of a plurality of EE controllers of the apparatus,
wherein the plurality of EE controllers correspond to a plurality of contexts, and
wherein each EE controller is configured to translate the target address when a context ID of the indirect access command corresponds to the context of that EE controller.

7. The apparatus of claim 6 , wherein the context ID includes a value expressed on the control path address bus of the control path.

8. The apparatus of claim 7 ,
wherein the indirect access command includes access domain information, and
wherein the context ID is a combination of the value expressed on the control path address bus and the access domain information.

9. The apparatus of claim 1 , further comprising:
a command translator configured to:
receive output of the EE controller, and
prepare the indirect access command for transmission to the DRAM device, wherein the DRAM controller is configured to:
transmit the prepared indirect access command to the DRAM device when it is determined that the indirect access command is to be allowed, and
block the prepared indirect access command from being transmitted to the DRAM device when it is determined that the indirect access command is to be blocked.

10. The apparatus of claim 1 , wherein each EE controller comprises:
a command decoder configured to decode the indirect access command received on the control path; and
a command/address converter configured to:
modify the decoded command and translate the target address, and
provide the modified command and the translated target address to the DRAM controller.

11. The apparatus of claim 1 ,
wherein the DRAM controller comprises an access controller, a command gate, and a DRAM interface,
wherein the access controller is configured to:
determine whether to allow or block the indirect access command based on the translated target address, and
enable/disable the command gate when it is determined that the indirect access command is to be allowed/blocked,

wherein the command gate is configured to:
receive a prepared command corresponding to the indirect access command from a command translator, and
provide the prepared command to the DRAM interface when enabled, and

wherein the DRAM interface is configured to issue the prepared command to the DRAM device when provided from the command gate.

12. The apparatus of claim 11 ,
wherein the access controller comprises a comparator and an address blacklist,
wherein the address blacklist is configured to store information regarding allowed/disallowed areas of the DRAM device, and
wherein the comparator is configured to:
compare the translated target address with the allowed/disallowed areas stored in the address blacklist, and
enable/disable the command gate based on the comparison.

13. The apparatus of claim 11 ,
wherein the DRAM interface comprises a DRAM command generator and a PHY interface,
wherein the DRAM command generator is configured to generate a DRAM command corresponding to the prepared command, the DRAM command being generated in a protocol and format understandable by the DRAM device, and
wherein the PHY interface is configured to transmit the generated DRAM command to the DRAM device over the DRAM link.

14. The apparatus of claim 13 , wherein the PHY interface is configured to transmit the generated DRAM command over the DRAM link in compliance with one or more memory bus standards.

15. The apparatus of claim 14 , wherein the one or more memory bus standards includes a low power double data rate 5 (LPDDR5) bus protocol.

16. The apparatus of claim 1 , further comprising one from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and an automotive vehicle incorporating the EE controller, the DRAM controller, the DRAM link, and the DRAM device.

17. The apparatus of claim 1 , wherein the DRAM controller is further configured to:
receive a direct access command on the data path comprising a data path data bus and a data path address bus, a data value of the direct access command being expressed on the data path data bus and a target address of the direct access command being expressed on the data path address bus,
determine whether to allow or block the direct access command based on the target address of the direct access command,
transmit the direct access command to the DRAM device when it is determined that the direct access command is to be allowed, and
block the direct access command from being transmitted to the DRAM device when it is determined that the direct access command is to be blocked.

18. A method comprising:
receiving, by an execution engine access (EE) controller of a host, an indirect access command on a control path comprising a control path data bus and a control path address bus, the indirect access command being a command to access a Dynamic Random Access Memory (DRAM) device and in which at least a part of the command is received on a path other than on a data path;
translating, by the EE controller, a target address of the indirect access command expressed on the control path data bus;
determining, by a DRAM controller of the host, whether to allow or block the indir

Assignees

• Qualcomm Inc

Inventors

• Chun Dexter Tamio
• Li Yanru

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F21/74

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

• G11C8/10

  Decoders · CPC title

• G06F2221/2141

  Access rights, e.g. capability lists, access control lists, access tables, access matrices · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title