Selective volatile memory refresh via memory-side data valid indication

Patent metadata

Field	Value
Publication number	US-10878880-B2
Application number	US-201816137496-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Sep 20, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Systems, methods, and computer programs are disclosed for refreshing a volatile memory. An embodiment of a method comprises storing, in a volatile memory device comprising a cell array having a plurality of rows with a corresponding row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses. The data valid indicator specifies that the corresponding row is in use, and the data invalid indicator specifies that the corresponding row is not in use. A memory controller initiates a refresh command. In response to the refresh command, the rows having the data valid indicator are refreshed while the rows having the data invalid indicator are skipped.

First claim

What is claimed is:

1. A method for refreshing a volatile memory, the method comprising:
storing, in a volatile memory device comprising a cell array having a plurality of rows with a corresponding row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses, the data valid indicator specifying that the corresponding row is in use and the data invalid indicator specifying that the corresponding row is not in use;
initiating a refresh command from a memory controller;
in response to the refresh command, refreshing the rows having the data valid indicator while skipping the rows having the data invalid indicator; and
updating the table stored in the volatile memory based on a current valid page list;
wherein updating the table comprises:
a kernel memory manager providing the current valid page list to a memory driver;
the memory driver converting one or more physical addresses to one or more of the row addresses; and
a memory controller sending an update command to the volatile memory device.

2. The method of claim 1 , wherein the volatile memory device comprises a dynamic random access memory (DRAM) device.

3. The method of claim 2 , wherein the DRAM device comprises a plurality of DRAM banks.

4. The method of claim 1 , wherein the refresh command comprises an auto-refresh command having an ignore flag.

5. The method of claim 1 , further comprising:
caching the table in a memory controller residing on a system on chip electrically coupled to the volatile memory device.

6. A system for refreshing a volatile memory, the system comprising:
means for storing, in a volatile memory device comprising a cell array having a plurality of rows with a corresponding row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses, the data valid indicator specifying that the corresponding row is in use and the data invalid indicator specifying that the corresponding row is not in use;
means for initiating a refresh command;
means for refreshing, in response to the refresh command, the rows having the data valid indicator while skipping the rows having the data invalid indicator; and
means for updating the table stored in the volatile memory based on a current valid page list;
wherein the means for updating the table comprises:
a kernel memory manager configured to provide the current valid page list to a memory driver;
the memory driver configured to convert one or more physical addresses to one or more of the row addresses; and
a memory controller sending an update command to the volatile memory device.

7. The system of claim 6 , wherein the data valid indicator and the data invalid indicator comprises a valid/invalid bit.

8. The system of claim 6 , wherein the volatile memory device comprises a dynamic random access memory (DRAM) device.

9. The system of claim 8 , wherein the DRAM device comprises a plurality of DRAM banks.

10. The system of claim 6 , wherein the means for initiating the refresh command comprises a memory controller residing on a system on chip electrically coupled to the volatile memory device, and the refresh command comprises an auto-refresh command, wherein the volatile memory device follows or ignores the data valid indicator and the data invalid indicator according to an ignore flag specified in the auto-refresh command.

11. The system of claim 6 , further comprising:
means for caching the table in a memory controller residing on a system on chip electrically coupled to the volatile memory device.

12. A computer program embodied in a computer readable medium and executed by a processor for refreshing a volatile memory, the computer program comprising logic configured to:
store, in a volatile memory device comprising a cell array having a plurality of rows with a corresponding row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses, the data valid indicator specifying that the corresponding row is in use and the data invalid indicator specifying that the corresponding row is not in use;
initiate a refresh command from a memory controller;
in response to the refresh command, refresh the rows having the data valid indicator while skipping the rows having the data invalid indicator; and
update the table stored in the volatile memory based on a current valid page list and by sending an update data valid bit map (VUPDATE) command to the volatile memory, wherein the VUPDATE command specifies a sector and one or more row validity bits.

13. The computer program of claim 12 , wherein the volatile memory device comprises a dynamic random access memory (DRAM) device having a plurality of DRAM banks.

14. The computer program of claim 12 , wherein the refresh command comprises an auto-refresh command.

15. The computer program of claim 12 , wherein the logic configured to update the table comprises:
a kernel memory manager providing the current valid page list to a memory driver; and
the memory driver converting one or more physical addresses to one or more of the row addresses; and
a memory controller sending an update command to the volatile memory device.

16. The computer program of claim 12 , further comprising logic configured to:
cache the table in a memory controller residing on a system on chip electrically coupled to the volatile memory device.

17. A system for refreshing volatile memory, the system comprising:
a system on chip (SoC) comprising a memory controller; and
a volatile random access memory electrically coupled to the memory controller, the volatile random access memory comprising:
a cell array having a plurality of rows with a corresponding row address; and
a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses, the data valid indicator specifying that the corresponding row is in use and the data invalid indicator specifying that the corresponding row is not in use;

wherein the volatile random access memory is configured to refresh, in response to a refresh command from the memory controller, the rows having the data valid indicator while skipping the rows having the data invalid indicator;
wherein the memory controller is configured to update the table stored in the volatile random access memory based on a current valid page list;
wherein the SoC comprises a kernel memory manager configured to provide the current valid page list to a memory driver, the memory driver converting one or more physical addresses to one or more of the row addresses, and the memory controller configured to send an update command to the volatile random access memory.

18. The system of claim 17 , wherein the volatile random access memory comprises a dynamic random access memory (DRAM) device.

19. The system of claim 18 , wherein the DRAM device comprises a plurality of DRAM banks.

20. The system of claim 17 , wherein the refresh command comprises an auto-refresh command.

21. The system of claim 17 , wherein the memory controller caches the table.

22. The system of claim 17 , wherein the data valid indicator and the data invalid indicator comprise a valid/invalid bit.

23. The system of claim 17 , wherein the volatile random access memory comprises a refresh controller in communication with the table.

Assignees

• Qualcomm Inc

Inventors

• Li Yanru
• Chun Dexter
• Patel Pratik

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40622 Primary

  Partial refresh of memory arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title