Selectable boot CPU

Patent metadata

Field	Value
Publication number	US-10599442-B2
Application number	US-201715448232-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Mar 2, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

First claim

What is claimed is:

1. A method of operating a system-on-chip (SoC), the method comprising:
selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of a quality of the plurality of CPU cores stored on the SoC,
wherein the information indicative of the quality of the plurality of CPU cores indicates a first cache associated with a first CPU core is not functional,
wherein the first CPU core is not selected to boot the SoC based on the first cache associated with the first CPU core not being functional;

running boot code on the selected CPU core;
allocating a second cache to the first CPU core,
wherein in response to allocating the second cache to the first CPU core, updating the information indicative of the quality of the plurality of CPU cotes to indicate that the first CPU core operates at a reduced performance level:

utilizing the first CPU core having the allocated second cache for operations other than running the moot code.

2. The method of claim 1 , wherein the information indicative of the quality of the plurality of CPU cores is based on a screening of the plurality of CPU cores.

3. The method of claim 1 , further comprising allocating resources on the SoC to the plurality of CPU cores based on the information indicative of the quality of the plurality of CPU cores.

4. The method of claim 3 , wherein the resources comprise at least one cache.

5. The method of claim 1 , further comprising storing the information indicative of the quality of the plurality of CPU cores in one or more efuses.

6. The method of claim 5 , wherein a blown efuse indicates a corresponding CPU core is not functional.

7. The method of claim 5 , wherein each of the one or more efuses is associated with an identifier of a CPU core stored in a memory.

8. The method of claim 1 , further comprising passing the information indicative of the quality of the plurality of CPU cores to an operating system executing on the SoC.

9. A system-on-chip (SoC) comprising:
a plurality of CPU cores;
a storage configured to store information indicative of a quality of the plurality of CPU cores; and
circuitry configured to:
select a CPU core to boot the SoC based on the information indicative of the quality of the plurality of CPU cores,
wherein the information indicative of the quality of the plurality of CPU cores indicates a first cache associated with a first CPU core is not functional,
wherein the first CPU core is not selected to boot the SoC based on the first cache associated with the first CPU core not being functional,
wherein boot code is run on the selected CPU core; and

allocate a second cache to the first CPU core,
wherein in response to allocating the second cache to the first CPU core, update the information indicative of the quality of the plurality of CPU cores to indicate that the first CPU core operates at a reduced performance level,
wherein the first CPU core having the allocated second cache is utilized for operations other than running boot code.

10. The SoC of claim 9 , wherein the information indicative of the quality of the plurality of CPU cores is based on a screening of the plurality of CPU cores.

11. The SoC of claim 9 , wherein the storage is further configured to store information regarding allocating resources on the SoC to the plurality of CPU cores.

12. The SoC of claim 11 , wherein the resources comprise at least one cache.

13. The SoC of claim 9 , wherein the storage comprises one or more efuses.

14. The SoC of claim 13 , wherein a blown efuse indicates a corresponding CPU core is not functional.

15. The SoC of claim 13 , wherein each of the one or more efuses is associated with an identifier of a CPU core stored in a memory.

16. The SoC of claim 9 , wherein the circuitry is further configured to pass the information indicative of the quality of the plurality of CPU cores to an operating system executing on the SoC.

17. A system-on-chip (SoC) comprising:
means for storing information indicative of a quality of a plurality of CPU cores of the SoC;
means for selecting a CPU core to boot the SoC based on the information indicative of the quality of the plurality of CPU cores,
wherein the information indicative of the quality of the plurality of CPU cores indicates a first cache associated with a first CPU core is not functional,
wherein the first CPU core is not selected to boot the SoC based on the first cache associated with the first CPU core not being functional;

means for allocating a second cache to the first CPU core,
wherein in response to allocating the second cache to the first CPU core, updating the information indicative of the quality of the plurality of CPU cores to indicate that the first CPU core operates at a reduced performance level;

means for running boot code on the selected CPU core; and
means for utilizing the first CPU core having the allocated second cache for operations other than running the boot code.

18. A non-transitory computer readable medium having instructions stored thereon for causing a system-on-chip (SoC) to perform a method, the method comprising:
selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of a quality of the plurality of CPU cores stored on the SoC,
wherein the information indicative of the quality of the plurality of CPU cores indicates a first cache associated with a first CPU core is not functional,
wherein the first CPU core is not selected to boot the SoC based on the first cache associated with the first CPU core not being functional;

allocating a second cache to the first CPU core,
wherein in response to allocating the second cache to the first CPU core, updating the information indicative of the quality of the plurality of CPU cores to indicate that the first CPU core operates at a reduced performance level:

running boot code on the selected CPU core; and
utilizing the first CPU core having the allocated second cache for operations other than running the boot code.

Assignees

• Qualcomm Inc

Inventors

• Packer Ali Dhamim
• Li Yanru
• Shrivastava Ashutosh
• Touzni Azzedine
• Desai Mamta

Classifications

• G06F9/4403 Primary

  Processor initialisation · CPC title