Caching lookup tables for block family error avoidance
US-12591475-B2 · Mar 31, 2026 · US
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Ish Mark patents
Ish Mark is listed as an inventor on 139 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ish Mark |
| Total patents | 139 |
| First publication | Jan 22, 2015 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatus with response completion pacing
US-2026050381-A1 · Feb 19, 2026 · US
Namespace management for memory sub-systems
US-2025355802-A1 · Nov 20, 2025 · US
Apparatus with response completion pacing
US-12468449-B2 · Nov 11, 2025 · US
Namespace management for memory sub-systems
US-12393510-B2 · Aug 19, 2025 · US
Dynamic selection of cores for processing responses
US-2025181274-A1 · Jun 5, 2025 · US
Suspending memory erase operations to perform higher priority memory commands
US-2025182829-A1 · Jun 5, 2025 · US
Memory management among multiple erase blocks coupled to a same string
US-2025077415-A1 · Mar 6, 2025 · US
Suspending memory erase operations to perform higher priority memory commands
US-12230332-B2 · Feb 18, 2025 · US
Dynamic selection of cores for processing responses
US-12182447-B2 · Dec 31, 2024 · US
Recent patents
Latest publications not already listed above.
Caching lookup tables for block family error avoidance
US-2024419523-A1 · Dec 19, 2024 · US
Multi-Pass Data Programming in a Memory Sub-System having Multiple Dies and Planes
US-2024377991-A1 · Nov 14, 2024 · US
Apparatus with response completion pacing
US-2024354006-A1 · Oct 24, 2024 · US
Caching lookup tables for block family error avoidance
US-12079065-B2 · Sep 3, 2024 · US
Apparatus with response completion pacing
US-12050776-B2 · Jul 30, 2024 · US
Multi-pass data programming in a memory sub-system having multiple dies and planes
US-12050809-B2 · Jul 30, 2024 · US
Logical unit number queues and logical unit number queue scheduling for memory devices
US-2024248647-A1 · Jul 25, 2024 · US
Logical unit number queues and logical unit number queue scheduling for memory devices
US-11966635-B2 · Apr 23, 2024 · US
Implementing automatic rate control in a memory sub-system
US-11960740-B2 · Apr 16, 2024 · US
Logical unit number queues and logical unit number queue scheduling for memory devices
US-2024069808-A1 · Feb 29, 2024 · US
Caching lookup tables for block family error avoidance
US-2024069997-A1 · Feb 29, 2024 · US
Suspending memory erase operations to perform higher priority memory commands
US-2024071520-A1 · Feb 29, 2024 · US
Partial Execution of a Write Command from a Host System
US-2024036768-A1 · Feb 1, 2024 · US
Memory sub-system management of firmware block record and device block record
US-11847065-B2 · Dec 19, 2023 · US
Apparatus with response completion pacing
US-2023393750-A1 · Dec 7, 2023 · US
Namespace management for memory sub-systems
US-2023350798-A1 · Nov 2, 2023 · US
Partial execution of a write command from a host system
US-11782643-B2 · Oct 10, 2023 · US
Firmware execution profiling and verification
US-11720681-B2 · Aug 8, 2023 · US
Block family tracking for memory devices
US-11720289-B2 · Aug 8, 2023 · US
Input/output size control between a host system and a memory sub-system
US-11709632-B2 · Jul 25, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 80 |
| Seagate Technology Llc | 44 |
| Lsi Corp | 11 |
| Avago Technologies General Ip | 11 |
| Ish Mark | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0679 | 70 |
| G06F3/0659 | 62 |
| G06F3/061 | 59 |
| G06F12/0246 | 58 |
| G06F2212/7201 | 42 |