Caching lookup tables for block family error avoidance

Patent metadata

Field	Value
Publication number	US-12079065-B2
Application number	US-202217931937-A
Country	US
Kind code	B2
Filing date	Sep 14, 2022
Priority date	Aug 31, 2022
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.

First claim

What is claimed is:

1. A memory device, comprising:
one or more components configured to:
determine a subset of one or more block family error avoidance (BFEA) lookup tables associated with a first memory location of the memory device, wherein the one or more BFEA lookup tables are stored in a second memory location of the memory device that is different from the first memory location;
cache the subset of the one or more BFEA lookup tables in the first memory location;
receive a read command associated with host data associated with the first memory location, wherein the host data is associated with a block family;
determine, based on the block family and the subset of the one or more BFEA tables cached in the first memory location, a threshold voltage offset associated with the host data;
compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data; and
read, using the modified threshold voltage, the host data from the first memory location.

2. The memory device of claim 1 , wherein determining the threshold voltage offset associated with the host data includes associating a block family identifier associated with the host data with the threshold voltage offset based on the subset of the one or more BFEA tables cached in the first memory location.

3. The memory device of claim 1 , wherein the one or more components are further configured to:
receive an indication that threshold voltage offset information associated with the block family has been updated; and
synchronize the subset of the one or more BFEA lookup tables with the threshold voltage offset information associated with the block family based on the indication.

4. The memory device of claim 3 , wherein the one or more components are further configured to:
receive another read command associated with host data;
determine, based on the block family and the subset of the one or more BFEA tables cached in the first memory location, another threshold voltage offset associated with the host data, wherein the other threshold voltage offset is different than the threshold voltage offset;
compute another modified threshold voltage by applying the other threshold voltage offset to the base read level voltage associated with the host data; and
read, using the other modified threshold voltage, the host data from the first memory location.

5. The memory device of claim 1 , wherein the block family includes a plurality of blocks that are associated with at least one of a time window during which the host data was written to the first memory location or a temperature window at which the host data was written to the first memory location.

6. The memory device of claim 1 , wherein the one or more components are further configured to:
determine, based on a period of time elapsing, that threshold voltage offset information associated with the block family should be updated; and
update the threshold voltage offset information by updating the one or more BFEA lookup tables associated with the second memory location.

7. The memory device of claim 1 , wherein the one or more BFEA lookup tables include at least a block partition table and a block family table, and wherein the subset of the one or more BFEA tables cached in the first memory location includes a first subset of the block partition table and a second subset of the block family table.

8. A memory device, comprising:
memory including at least a first memory location and a second memory location; and
a plurality of controllers operatively coupled to the memory and including at least a low-level controller associated with the first memory location and a high-level controller associated with the second memory location, the plurality of controllers configured to:
receive a write command associated with host data;
write the host data to the first memory location;
associate the host data with a block family based on at least one of a time window during which the host data was written to the first memory location or a temperature window at which the host data was written to the first memory location;
store, in one or more block family error avoidance (BFEA) lookup tables associated with the second memory location, information associating the host data with the block family and associating a threshold voltage offset with the block family, wherein the one or more BFEA lookup tables are associated with multiple block families;
cache a subset of the one or more BFEA lookup tables associated with the block family in the first memory location; and
read the host data from the first memory location using a modified threshold voltage that is obtained based on applying the threshold voltage offset to a base read level voltage associated with the host data.

9. The memory device of claim 8 , wherein the plurality of controllers are further configured to:
receive a read command associated with host data;
determine, based on the block family and the subset of the one or more BFEA tables cached in the first memory location, the threshold voltage offset associated with the host data; and
compute the modified threshold voltage by applying the threshold voltage offset to the base read level voltage.

10. The memory device of claim 9 , wherein determining the threshold voltage offset associated with the host data includes associating a block family identifier associated with the host data with the threshold voltage offset based on the subset of the one or more BFEA tables cached in the first memory location.

11. The memory device of claim 9 , wherein the plurality of controllers are further configured to:
receive an indication that threshold voltage offset information associated with the block family has been updated; and
synchronize the subset of the one or more BFEA lookup tables with the threshold voltage offset information associated with the block family based on the indication.

12. The memory device of claim 11 , wherein the plurality of controllers are further configured to:
receive another read command associated with host data;
determine, based on the block family and the subset of the one or more BFEA tables cached in the first memory location, another threshold voltage offset associated with the host data, wherein the other threshold voltage offset is different than the threshold voltage offset;
compute another modified threshold voltage by applying the other threshold voltage offset to the base read level voltage associated with the host data; and
read, using the other modified threshold voltage, the host data from the first memory location.

13. The memory device of claim 8 , wherein the block family includes a plurality of blocks that are associated with the at least one of the time window during which the host data was written to the first memory location or the temperature window at which the host data was written to the first memory location.

14. The memory device of claim 8 , wherein the plurality of controllers are further configured to:
determine, based on a period of time elapsing, that threshold voltage offset information associated with the block family should be updated; and
update the threshold voltage offset information by updating the one or more BFEA lookup tables associated with the second memory location.

15. The memory device of claim 8 , wherein the one or more BFEA lookup tables include at least a block partition table and a block family table, and wherein the subset of the one or more BFEA tables cached in the first memory location includes a first subset of the block partition table and a se

Assignees

• Micron Technology Inc

Inventors

• Bukhari Shakeel Isamohiuddin
• Ish Mark

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021 Primary

  in voltage or current generators · CPC title

• G06F12/0215

  with look ahead addressing means · CPC title

• G06F12/12

  Replacement control · CPC title

• G06F2212/251

  Local memory within processor subsystem · CPC title