Multi-pass data programming in a memory sub-system having multiple dies and planes

Patent metadata

Field	Value
Publication number	US-12050809-B2
Application number	US-202217675888-A
Country	US
Kind code	B2
Filing date	Feb 18, 2022
Priority date	Jun 14, 2019
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

First claim

What is claimed is:

1. A device, comprising:
memory cells configured on a plurality of units operable in parallel to perform write operations; and
logic circuit configured to:
identify, for a command to write data into the memory cells, a portion of the memory cells to store the data;
generate, for the command, a media layout of mapping logical addresses of the data to physical addresses of the portion of the memory cells identified for the data to be written according to the command; and
perform an atomic multi-pass programming operation configured to use separate units in parallel in writing the data in execution of the command;

wherein the logic circuit is further configured to:
queue the command among commands received from a host system;
allocate at least two pages of memory cells to store the data responsive to the commands based on availability of the at least two pages to data programming operations; and
receive the data from the host system, after allocation of the at least two pages to store the data to be written according to the command;

wherein a first page in the at least two pages is in a first integrated circuit die; and a second page in the at least two pages is in a second integrated circuit die;
wherein the atomic multi-pass programming operation includes a first pass programming of the first page and a second pass programming of the second page;
wherein the first pass programming is in a first mode; and the second pass programming is in a second mode; and
wherein the first mode and the second mode are different ones of:
a single level cell (SLC) mode;
a multi-level cell (MLC) mode;
a triple level cell (TLC) mode; and
a quad-level cell (QLC) mode.

2. The device of claim 1 , wherein the allocation is configured to minimize a mismatch between a storage capacity of the at least two pages programmed in the atomic multi-pass programming operation and a size of the data identified by the command.

3. The device of claim 2 , wherein the at least two pages are allocated from a block set configured to be erased together.

4. The device of claim 3 , wherein the allocation is based on programming modes of memory cells identified for next available pages in block sets.

5. A method, comprising:
identifying, for a command to write data into memory cells configured on a plurality of units operable in parallel to perform write operations, a portion of the memory cells to store the data;
generating, for the command, a media layout of mapping logical addresses of the data to physical addresses of the portion of the memory cells identified for the data to be written according to the command; and
performing an atomic multi-pass programming operation configured to use the separate units in parallel in writing the data in execution of the command;
wherein the atomic multi-pass programming operation includes a first pass programming of a first page in a first mode and a second pass programming of a second page in a second mode; and wherein the first mode and the second mode are different ones of:
a single level cell (SLC) mode;
a multi-level cell (MLC) mode;
a triple level cell (TLC) mode; and
a quad-level cell (QLC) mode.

6. The method of claim 5 , wherein the first page is in a first integrated circuit die; and the second page is in a second integrated circuit die.

7. The method of claim 5 , further comprising:
queuing the command among commands received from a host system;
allocating at least two pages of memory cells to store the data responsive to the commands based on availability of the at least two pages to data programming operations; and
receiving the data from the host system, after allocation of the at least two pages to store the data to be written according to the command.

8. The method of claim 7 , wherein the allocation is configured to minimize a mismatch between a storage capacity of the at least two pages programmed in the atomic multi-pass programming operation and a size of the data identified in the command.

9. The method of claim 8 , wherein the at least two pages are allocated from a block set configured to be erased together.

10. The method of claim 9 , wherein the allocation is based on programming modes of memory cells identified for next available pages in block sets.

11. A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, causes the memory sub-system to perform a method, the method comprising:
identifying, for a command to write data into memory cells configured on a plurality of units operable in parallel to perform write operations, a portion of the memory cells to store the data;
generating, for the command, a media layout of mapping logical addresses of the data to physical addresses of the portion of the memory cells identified for the data to be written according to the command; and
performing an atomic multi-pass programming operation configured to use the separate units in parallel in writing the data in execution of the command;
wherein the atomic multi-pass programming operation includes a first pass programming of a first page in a first mode and a second pass programming of a second page in a second mode; and
wherein the first mode and the second mode are different ones of:
a single level cell (SLC) mode;
a multi-level cell (MLC) mode;
a triple level cell (TLC) mode; and
a quad-level cell (QLC) mode.

Assignees

• Micron Technology Inc

Inventors

• Subbarao Sanjay
• Williams Steven S
• Ish Mark
• Maroney John Edward

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F12/10

  Address translation · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title