Apparatus with response completion pacing

Patent metadata

Field	Value
Publication number	US-12468449-B2
Application number	US-202418759793-A
Country	US
Kind code	B2
Filing date	Jun 28, 2024
Priority date	Jun 1, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

First claim

We claim:

1 . A memory device, comprising:
a ready response queue configured to store data; a processing logic operably coupled to the ready response queue and configured to:
track a duration for sending command responses to a device;
determine a target number of responses in the ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue; and
send a response from the ready response queue to the device based on the duration and a number of responses in the ready response queue relative to the target number of responses.

2 . The memory device of claim 1 , wherein the processing logic operably coupled to the ready response queue is configured to determine the number of responses in the ready response queue is less than the target number of responses in the ready response queue.

3 . The memory device of claim 2 , wherein the processing logic operably coupled to the ready response queue is configured to:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determine that a time gap between when the response was sent and a current time, does not exceed a predetermined delay time; and reset a pacing logic timer, wherein the pacing logic timer tracks the duration for sending the command responses to the device.

4 . The memory device of claim 2 , wherein the processing logic operably coupled to the ready response queue is configured to:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determine that a time gap between when the response was sent and a current time exceeds a predetermined delay time; and send a second response from the ready response queue to the device.

5 . The memory device of claim 1 , wherein the processing logic operably coupled to the ready response queue is configured to:
determine that the target number of responses in the ready response queue exceeds the number of responses in the ready response queue; and adjust a cadence period of output response completions.

6 . The memory device of claim 1 , wherein the ready response queue is a first in first out (FIFO) queue, wherein the processing logic operably coupled to the ready response queue is configured to maintain the FIFO queue to hold and delay responses for completed commands according to one or more cadenced response timings.

7 . A memory controller, comprising:
at least one processor; and embedded memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions comprising:
tracking a duration for sending command responses to a device;
determining a target number of responses in a ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue; and
sending a response from the ready response queue to the device based on the duration and a number of responses in the ready response queue relative to the target number of responses.

8 . The memory controller of claim 7 , wherein the instructions include:
determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue.

9 . The memory controller of claim 8 , wherein the instructions include:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time, does not exceed a predetermined delay time; and resetting a pacing logic timer, wherein the pacing logic timer tracks the duration for sending the command responses to the device.

10 . The memory controller of claim 8 , wherein the instructions include:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time exceeds a predetermined delay time; and sending a second response from the ready response queue to the device.

11 . The memory controller of claim 7 , wherein the instructions include:
determining that the target number of responses in the ready response queue exceeds the number of responses in the ready response queue; and adjusting a cadence period of output response completions.

12 . The memory controller of claim 7 , wherein the ready response queue is a first in first out (FIFO) queue, wherein the instructions include maintaining the FIFO queue to hold and delay responses for completed commands according to one or more cadenced response timings.

13 . A method of response completion pacing for latency control, the method comprising:
tracking a duration for sending command responses to a device; determining a target number of responses in a ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue; and sending a response from the ready response queue to the device based on the duration and a number of responses in the ready response queue relative to the target number of responses.

14 . The method of claim 13 , further comprising:
determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue.

15 . The method of claim 14 , further comprising:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time, does not exceed a predetermined delay time; and resetting a pacing logic timer, wherein the pacing logic timer tracks the duration for sending the command responses to the device.

16 . The method of claim 14 , further comprising:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time exceeds a predetermined delay time; and sending a second response from the ready response queue to the device.

17 . The method of claim 13 , further comprising:
determining that the target number of responses in the ready response queue exceeds the number of responses in the ready response queue; and adjusting a cadence period of output response completions.

Assignees

• Micron Technology Inc

Inventors

• Huang Ying
• Ish Mark

Classifications

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title