Apparatus with response completion pacing

Patent metadata

Field	Value
Publication number	US-12050776-B2
Application number	US-202218049973-A
Country	US
Kind code	B2
Filing date	Oct 26, 2022
Priority date	Jun 1, 2022
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

First claim

We claim:

1. A method of response completion pacing for latency control, the method comprising:
determining that a pacing logic timer has expired, wherein the pacing logic timer tracks a cadenced duration for periodically sending command responses generated by a memory array to a host device; and
sending a response from a ready response queue to the host device based on the determination that the pacing logic timer has expired and a number of responses in the ready response queue relative to a target number of responses.

2. The method of claim 1 , further comprising:
determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue.

3. The method of claim 2 , further comprising:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time, does not exceed a predetermined delay time; and
resetting the pacing logic timer.

4. The method of claim 2 , further comprising:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time exceeds a predetermined delay time; and
sending a second response from the ready response queue to the host device.

5. The method of claim 1 , further comprising:
determining the target number of responses in the ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue.

6. The method of claim 1 , further comprising:
determining that the target number of responses in the ready response queue exceeds the number of responses in the ready response queue; and
adjusting a cadence period of output response completions.

7. A memory device, comprising:
a ready response queue configured to store processing results generated by a memory array;
a processing logic operably coupled to the ready response queue and configured to:
determine that a pacing logic timer has expired, wherein the pacing logic timer tracks a cadenced duration for periodically sending command responses generated by the memory array to a host device; and
send a response from the ready response queue to the host device based on the determination that the pacing logic timer has expired and a number of responses in the ready response queue relative to a target number of responses.

8. The memory device of claim 7 , wherein the processing logic operably coupled to the ready response queue is configured to determine the number of responses in the ready response queue is less than the target number of responses in the ready response queue.

9. The memory device of claim 8 , wherein the processing logic operably coupled to the ready response queue is configured to:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determine that a time gap between when the response was sent and a current time, does not exceed a predetermined delay time; and
reset the pacing logic timer.

10. The memory device of claim 8 , wherein the processing logic operably coupled to the ready response queue is configured to:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determine that a time gap between when the response was sent and a current time exceeds a predetermined delay time; and
send a second response from the ready response queue to the host device.

11. The memory device of claim 7 , wherein the processing logic operably coupled to the ready response queue is configured to:
determine the target number of responses in the ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue.

12. The memory device of claim 7 , wherein the processing logic operably coupled to the ready response queue is configured to:
determine that the target number of responses in the ready response queue exceeds the number of responses in the ready response queue; and
adjust a cadence period of output response completions.

13. The memory device of claim 7 , wherein the ready response queue is a first in first out (FIFO) queue, wherein the processing logic operably coupled to the ready response queue is configured to maintain the FIFO queue to hold and delay responses for completed commands according to one or more cadenced response timings.

14. A memory controller, comprising:
a memory array including memory cells configured to store data;
at least one processor coupled to the memory array;
embedded memory coupled to the processor and storing instructions for execution by the at least one processor, the instructions comprising:
determining that a pacing logic timer has expired, wherein the pacing logic timer tracks a cadenced duration for periodically sending command responses generated by the memory array to a host device; and
sending a response from a ready response queue to the host device based on the determination that the pacing logic timer has expired and a number of responses in the ready response queue relative to a target number of responses.

15. The memory controller of claim 14 , wherein the processor instructions include:
determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue.

16. The memory controller of claim 15 , wherein the processor instructions include:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time, does not exceed a predetermined delay time; and
resetting the pacing logic timer.

17. The memory controller of claim 15 , wherein the processor instructions include:
in response to determining the number of responses in the ready response queue is less than the target number of responses in the ready response queue, determining that a time gap between when the response was sent and a current time exceeds a predetermined delay time; and
sending a second response from the ready response queue to the host device.

18. The memory controller of claim 14 , wherein the processor instructions include:
determining the target number of responses in the ready response queue based on a predetermined time gap between each response in the ready response queue and a depth of the ready response queue.

19. The memory controller of claim 14 , wherein the processor instructions include:
determining that the target number of responses in the ready response queue exceeds the number of responses in the ready response queue; and
adjusting a cadence period of output response completions.

20. The memory controller of claim 14 , wherein the ready response queue is a first in first out (FIFO) queue, wherein the processor instructions include maintaining the FIFO queue to hold and delay responses for completed commands according to one or more cadenced response timings.

Assignees

• Micron Technology Inc

Inventors

• Huang Ying
• Ish Mark

Classifications

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title