Semiconductor device design mitigating latch-up

Patent metadata

Field	Value
Publication number	US-12176289-B2
Application number	US-202217656368-A
Country	US
Kind code	B2
Filing date	Mar 24, 2022
Priority date	Mar 24, 2022
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first conductor extending in a first direction and configured to receive a first power supply signal, the first conductor is connected to a first electrode;
a second conductor extending in the first direction and configured to receive a second power supply signal, the second conductor is connected to a second electrode, the first conductor offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor, and wherein a first voltage value of the first power supply signal is greater than a second voltage of the second power supply signal;
a first output conductor extending in the first direction and connected to a third electrode;
a second output conductor extending in the first direction and offset from the first conductor in the second direction and connected to a fourth electrode, the first output conductor is connected to the second output conductor; and
a first gate conductor disposed between the first conductor the first output conductor, and between the second conductor and the second output conductor, disposed on the first electrode, the second electrode, the third electrode and the fourth electrode, and configured to receive an input signal.

2. The semiconductor device of claim 1 , wherein the first conductor is disposed along a first side of the first gate conductor and the second conductor is disposed along a second side of the first gate conductor, the second side is opposite the first side.

3. The semiconductor device of claim 2 , wherein the first conductor is disposed at a first end of the first gate conductor and the second conductor is disposed at a second end of the first gate conductor, the first end is opposite the second end.

4. The semiconductor device of claim 1 , wherein the first conductor is disposed opposite the second output conductor and the second conductor is disposed opposite the first output conductor.

5. The semiconductor device of claim 1 further comprising a substrate, wherein the first conductor is disposed on a first region of the substrate and the second conductor is disposed on a second region of the substrate, wherein the first region is associated with a first side of the substrate and the second region is associated with a second side of the substrate opposite the first side.

6. The semiconductor device of claim 1 further comprising:
a P-type substrate comprising an N-well region, wherein the first electrode is a P-type electrode disposed within the N-well region, and the second electrode is an N-type electrode disposed within the P-type substrate.

7. The semiconductor device of claim 1 further comprising:
a third conductor configured to receive the first power supply signal and extending in the first direction, the third conductor is disposed on a fifth electrode;
a fourth conductor configured to receive the second power supply signal and extending in the first direction, the fourth conductor is disposed on a sixth electrode, wherein the third conductor is offset from the fourth conductor in the second direction; and
a second gate conductor is disposed between the third conductor and the fourth conductor, connected to the fifth electrode and the sixth electrode, and configured to receive the input signal.

8. The semiconductor device of claim 7 further comprising a third gate conductor disposed between the second conductor and the third conductor.

9. The semiconductor device of claim 1 , wherein the first conductor and the first output conductor are disposed along a first end of the first gate conductor.

10. The semiconductor device of claim 9 , wherein the second conductor and the second output conductor are disposed along a second end of the first gate conductor.

11. A semiconductor device comprising:
a first gate conductor configured to receive an input signal, the first gate conductor having a first side, a second side opposite the first side, a first end, and a second end opposite the first end, the first gate conductor is connected to a first electrode, a second electrode, a third electrode and a fourth electrode;
a first conductor connected to the first electrode, disposed along the first side and at the first end of the first gate conductor, and configured to receive a first power supply signal;
a second conductor connected to the second electrode, disposed along the second side and at the second end of the first gate conductor, and configured to receive a second power supply signal, wherein a first voltage value of the first power supply signal is greater than a second voltage of the second power supply signal, and wherein disposing the first conductor along the first side and at the first end of the first gate conductor, and disposing the second conductor along the second side and at the second end of the first conductor mitigates formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor;
a first output conductor disposed along the second side and at the first end of the first gate conductor and connected to the third electrode; and
a second output conductor disposed along the first side and at the second end of the first gate conductor and connected to the fourth electrode, the first output conductor is connected to the second output conductor.

12. The semiconductor device of claim 11 , wherein the first conductor is disposed opposite the second output conductor and the second conductor is disposed opposite the first output conductor.

13. The semiconductor device of claim 11 further comprising a substrate, wherein the first conductor is disposed in a first region of the substrate and the second conductor is disposed in a second region of the substrate, wherein the first region is associated with a first side of the substrate and the second region is associated with a second side of the substrate opposite the first side of the substrate.

14. The semiconductor device of claim 11 further comprising:
a P-type substrate comprising an N-well region, the first electrode is a P-type electrode disposed within the N-well region, and the second electrode is an N-type electrode disposed within the P-type substrate.

15. The semiconductor device of claim 11 further comprising:
a second gate conductor configured to receive the input signal, the second gate conductor having a first side, a second side opposite the first side, a first end, and a second end opposite the first end, the second gate conductor connected to a fifth electrode and a sixth electrode;
a third conductor connected to the fifth electrode, disposed along the first side and at the first end of the second gate conductor, and configured to receive the first power supply signal; and
a fourth conductor connected to the sixth electrode, disposed along the second side and at the second end of the second gate conductor, and configured to receive the second power supply signal.

16. The semiconductor device of claim 15 further comprising:
a third output conductor disposed along the second side and at the first end of the second gate conductor; and
a fourth output conductor disposed along the first side and at the second end of the second gate conductor.

17. A semiconductor device comprising:
first conductors disposed in a first region of the semiconductor device and configured to receive a first power supply signal;
second conductors di

Assignees

• IBM

Inventors

• Wolpert David
• Sigal Leon
• Hook Terence

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D84/991

  Latch-up prevention · CPC title

• H10D84/854

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title