Gate-all-around field effect transistor having multiple threshold voltages

Patent metadata

Field	Value
Publication number	US-12015069-B2
Application number	US-202016745049-A
Country	US
Kind code	B2
Filing date	Jan 16, 2020
Priority date	Jan 4, 2017
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

First claim

What is claimed is:

1. An apparatus, comprising:
a doped conducting channel region having at least two conducting layers including an n-type dopant for an n-type work function and at least two conducting layers including a p-type dopant for a p-type work function, the two conducting layers including a silicon n-type channel and a silicon germanium p-type channel; and
a gate stack surrounding all sides of the conducting channel region, wherein the gate stack comprises:
a doped substrate;
a metal doping layer deposited directly on the doped substrate, wherein the metal doping layer is formed from a dipole; and
an adjustment oxide layer deposited directly on the metal doping layer, wherein gate stack including the metal doping layer provides at least four threshold voltages for the apparatus, the apparatus being a single transistor having a single gate structure with the at least four threshold voltages, wherein differences in the threshold voltages is attributed to the metal doping, the metal doping for the n-type work function including a metal alloy selected from the group consisting of titanium aluminum and titanium aluminum carbide.

2. The apparatus of claim 1 , wherein the apparatus is an n-type field effect transistor.

3. The apparatus of claim 2 , wherein the substrate comprises silicon.

4. The apparatus of claim 3 , wherein the metal doping layer comprises at least one of: lanthanum, ytterbium, magnesium, an oxide of lanthanum, an oxide of ytterbium, and an oxide of magnesium.

5. The apparatus of claim 3 , further comprising:
a layer of a first barrier metal deposited directly on the adjustment oxide layer;
a layer of an n-type field effect transistor work function metal deposited directly on the layer of the first barrier metal; and
a layer of a second barrier metal deposited directly on the layer of the n-type field effect transistor work function metal.

6. The apparatus of claim 1 , wherein the apparatus is a p-type field effect transistor.

7. The apparatus of claim 1 , wherein the substrate comprises silicon germanium.

8. The apparatus of claim 7 , wherein the silicon germanium is p-doped.

9. The apparatus of claim 1 , wherein the gate stack directly contacts the doped conducting channel region.

10. The apparatus of claim 1 , wherein the gate stack has a plurality of threshold voltages that comprise up to eight threshold voltages.

11. The apparatus of claim 1 , wherein the doped conducting channel region comprises a plurality of conducting channels and at least some conducting channels of the plurality of conducting channels are epitaxially grown and doped in situ.

12. An apparatus, comprising:
an n-type field effect transistor, comprising:
a first doped conducting channel region having at least four conducting layers including an n-type dopant, the at least four conducting layers comprised of silicon; and
a first gate stack surrounding all sides of the first doped conducting channel region, wherein the first gate stack comprises:
a first doped substrate;
a first metal doping layer deposited directly on the first doped substrate, wherein the first metal doping layer is formed from a dipole; and
a first adjustment oxide layer deposited directly on the first metal doping layer; and

a p-type field effect transistor, comprising:
a second doped conducting channel region having at least four conducting layers including a p-type dopant, the at least four conducting layer comprised of silicon germanium; and
a second gate stack surrounding all sides of the second doped conducting channel region, wherein the second gate stack comprises:
a second doped substrate;
a second metal doping layer deposited directly on the second doped substrate, wherein the second metal doping layer is formed from a dipole; and
a second adjustment oxide layer deposited directly on the second metal doping layer, wherein the apparatus has a plurality of threshold voltages including at least four different n-type threshold voltages for the n-type field effect transistor that are attributed to the first metal doping layer and at least four different p-type threshold voltages for the p-type field effect transistor that are attributed to the second metal doping layer, the first metal doping layer including a metal alloy selected from the group consisting of titanium aluminum and titanium aluminum carbide.

13. The apparatus of claim 12 , wherein the first gate stack directly contacts the first doped conducting channel region and the second gate stack directly contacts the second conducting channel region.

14. The apparatus of claim 12 , wherein the apparatus has a plurality of threshold voltages that comprise up to eight n-type threshold voltages and up to eight p-type threshold voltages.

15. The apparatus of claim 12 , further comprising:
a layer of a first barrier metal deposited directly on the first adjustment oxide layer;
a layer of a p-type field effect transistor work function metal deposited directly on the layer of the first barrier metal; and
a layer of a second barrier metal deposited directly on the layer of the p-type field effect transistor work function metal.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Guillorn Michael A
• Hook Terence
• Robison Robert R
• Vega Reinaldo
• Yamashita Tenko

Classifications

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title