Heat pipe for vertically stacked field effect transistors

Patent metadata

Field	Value
Publication number	US-12040250-B2
Application number	US-202217841202-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Jun 15, 2022
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs.

First claim

What is claimed is:

1. A semiconductor structure comprising:
vertically stacked field effect transistors located in an electrically active device area of the semiconductor structure; and
an electrically inactive structure located in an electrically inactive device area of the semiconductor structure that is located adjacent to the electrically active device area of the semiconductor structure, wherein the electrically inactive structure comprises at least one vertical interconnect structure that continuously extends from an uppermost layer of the vertically stacked field effect transistors to a bottommost layer of the vertically stacked field effect transistors.

2. The semiconductor structure of claim 1 , wherein the vertically stacked field effect transistors comprise a p-type field effect transistor stacked above an n-type field effect transistor.

3. The semiconductor structure of claim 1 , wherein the vertically stacked field effect transistors comprise an n-type field effect transistor stacked above a p-type field effect transistor.

4. The semiconductor structure of claim 1 , wherein the vertically stacked field effect transistors comprise at least two n-type field effect transistors stacked one atop the other.

5. The semiconductor structure of claim 1 , wherein the vertically stacked field effect transistors comprise at least two p-type field effect transistors stacked one atop the other.

6. The semiconductor structure of claim 1 , wherein the vertically stacked field effect transistors comprise three or more field effect transistors stacked one atop the other.

7. The semiconductor structure of claim 1 , further comprising at least one dummy gate structure located in the electrically inactive device area of the semiconductor structure.

8. The semiconductor structure of claim 7 , wherein at least a portion of the at least one dummy gate structure extends continuously from an uppermost layer of the vertically stacked field effect transistors to a bottommost layer of the vertically stacked field effect transistors.

9. The semiconductor structure of claim 1 , further comprising at least one active device area vertical interconnect structure located in the electrically active device area of the semiconductor structure, and wherein the at least one active device area vertical interconnect structure extends from the uppermost layer to the bottommost layer of the vertically stacked field effect transistors and contacts portions of the vertically stacked field effect transistors.

10. The semiconductor structure of claim 9 , wherein the at least one active device area vertical interconnect structure has a substantially same shape as the at least one vertical interconnect structure that provides the electrically inactive structure.

11. The semiconductor structure of claim 9 , wherein the at least one active device area vertical interconnect structure has a different shape than the at least one vertical interconnect structure that provides the electrically inactive structure.

12. The semiconductor structure of claim 11 , wherein the at least one vertical interconnect structure that provides the electrically inactive structure is block shaped, and the electrically inactive device area is devoid of a dummy gate structure.

13. The semiconductor structure of claim 1 , further comprising at least one power bus located above, and electrically connected to, an uppermost field effect transistor of the vertically stacked field effect transistors.

14. The semiconductor structure of claim 1 , further comprising at least one power bus located below, and electrically connected to, and a bottommost field effect transistor of the vertically stacked field effect transistors.

15. The semiconductor structure of claim 1 , further comprising a semiconductor substrate located beneath the vertically stacked field effect transistors.

16. The semiconductor structure of claim 15 , wherein the at least one vertical interconnect structure is configured to dissipate heat generated by the vertically stacked field effect transistors into the semiconductor substrate.

17. The semiconductor structure of claim 1 , wherein the at least one vertical interconnect structure that provides the electrically inactive structure is composed of an electrically conductive metal or electrically conductive metal alloy.

Assignees

• IBM

Inventors

• Hook Terence
• Anderson Brent A
• Chou Anthony I

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W40/73 Primary

  for cooling by change of state · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title