Benchmark device on a semiconductor wafer with fuse element
US-2023116600-A1 · Apr 13, 2023 · US
Protection diode to prevent charge damage during MOL
US12550448B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12550448-B2 |
| Application number | US-202217947524-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2022 |
| Priority date | Sep 19, 2022 |
| Publication date | Feb 10, 2026 |
| Grant date | Feb 10, 2026 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.
First claim
Opening claim text (preview).
The invention claimed is: 1 . An integrated circuit comprising: a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts; and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, wherein the DUT is electrically connected to the protection diode by at least one gate contact. 2 . The integrated circuit of claim 1 , wherein the at least one gate contact includes a first gate contact and a second gate contact. 3 . The integrated circuit of claim 2 , wherein the first gate contact or one of the first S/D contacts electrically connects to a gate of the plurality of second gates of the DUT. 4 . The integrated circuit of claim 2 , wherein the second gate contact electrically connects to a S/D contact of the plurality of second S/D contacts of the DUT. 5 . The integrated circuit of claim 1 , wherein the protection diode is electrically connected to the DUT for gate oxide protection before M1 formation. 6 . The integrated circuit of claim 1 , wherein MOL layers connecting the protection diode to the DUT pertain to a planar field effect transistor (FET) structure. 7 . The integrated circuit of claim 1 , wherein MOL layers connecting the protection diode to the DUT pertain to a stacked FET structure. 8 . An integrated circuit comprising: a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts; and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, wherein the DUT is electrically connected to the protection diode by at least one additional S/D contact. 9 . The integrated circuit of claim 8 , wherein the at least one additional S/D contact includes a first additional S/D contact and a second additional S/D contact. 10 . The integrated circuit of claim 9 , wherein the first additional S/D contact electrically connects to a gate of the plurality of second gates of the DUT. 11 . The integrated circuit of claim 9 , wherein the second additional S/D contact electrically connects to a S/D contact of the plurality of second S/D contacts of the DUT. 12 . The integrated circuit of claim 8 , wherein the protection diode is electrically connected to the DUT for gate oxide protection before M1 formation. 13 . The integrated circuit of claim 8 , wherein MOL layers connecting the protection diode to the DUT pertain to a planar field effect transistor (FET) structure. 14 . The integrated circuit of claim 8 , wherein MOL layers connecting the protection diode to the DUT pertain to a stacked FET structure. 15 . An integrated circuit comprising: a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts; and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, wherein the DUT is electrically connected to the protection diode by at least one buried power rail (BPR). 16 . The integrated circuit of claim 15 , wherein the at least one BPR electrically connects to a first end of the plurality of second gates of the DUT. 17 . The integrated circuit of claim 15 , wherein the at least one BPR electrically connects to a second end of a portion of the plurality of second gates of the DUT. 18 . The integrated circuit of claim 15 , wherein the protection diode is electrically connected to the DUT for gate oxide protection before M1 formation. 19 . The integrated circuit of claim 15 , wherein MOL layers connecting the protection diode to the DUT pertain to a stacked FET structure. 20 . The integrated circuit of claim 15 , wherein MOL layers connecting the protection diode to the DUT pertain to a planar field effect transistor (FET) structure.
Assignees
Inventors
Classifications
- H10D89/921Primary
characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title
- H10D89/611Primary
using diodes as protective elements · CPC title
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Frequently asked questions
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- What does patent US12550448B2 cover?
- An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least …
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D89/921. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 10 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).