Systems and methods for integer-to-floating-point data transfers
US-2026086963-A1 · Mar 26, 2026 · US
This page is not indexed by search engines while we improve data quality.
Estlick Michael patents
Estlick Michael is listed as an inventor on 46 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Estlick Michael |
| Total patents | 46 |
| First publication | Apr 30, 2015 |
| Latest publication | Mar 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for executing an instruction by an arithmetic logic unit pipeline
US-2025390304-A1 · Dec 25, 2025 · US
Apparatuses, systems, and methods for out-of-order task resolution in integrated circuits
US-2025306939-A1 · Oct 2, 2025 · US
Apparatuses, systems, and methods for scheduling processor operations
US-2025306999-A1 · Oct 2, 2025 · US
Differential pipeline delays in a coprocessor
US-12333309-B2 · Jun 17, 2025 · US
Register based SIMD lookup table operations
US-12299445-B2 · May 13, 2025 · US
Split register list for renaming
US-12229563-B2 · Feb 18, 2025 · US
Methods and apparatus for providing mask register optimization for vector operations
US-12223324-B2 · Feb 11, 2025 · US
Thread forward progress and/or quality of service
US-12204935-B2 · Jan 21, 2025 · US
Distributed scheduler providing execution pipe balance
US-12118411-B2 · Oct 15, 2024 · US
Recent patents
Latest publications not already listed above.
Large number integer addition using vector accumulation
US-2024319964-A1 · Sep 26, 2024 · US
Apparatus and methods employing a shared read post register file
US-11960897-B2 · Apr 16, 2024 · US
Vector processing unit with programmable multicycle shuffle unit
US-2024111529-A1 · Apr 4, 2024 · US
Methods and apparatus for providing mask register optimization for vector operations
US-2024111526-A1 · Apr 4, 2024 · US
Bignum addition and/or subtraction with carry propagation
US-2024111489-A1 · Apr 4, 2024 · US
Systems and methods for interpolating register-based lookup tables
US-2024095180-A1 · Mar 21, 2024 · US
Methods and apparatus for managing register free lists
US-11907070-B2 · Feb 20, 2024 · US
Differential pipeline delays in a coprocessor
US-2024045694-A1 · Feb 8, 2024 · US
Split register list for renaming
US-2024004664-A1 · Jan 4, 2024 · US
Masked multi-lane instruction memory fault handling using fast and slow execution paths
US-11847463-B2 · Dec 19, 2023 · US
Multi-modal gather operation
US-11842200-B2 · Dec 12, 2023 · US
Register based simd lookup table operations
US-2023393855-A1 · Dec 7, 2023 · US
Differential pipeline delays in a coprocessor
US-11709681-B2 · Jul 25, 2023 · US
Method and apparatus for executing vector instructions with merging behavior
US-11573801-B1 · Feb 7, 2023 · US
Thread forward progress and/or quality of service
US-2023034933-A1 · Feb 2, 2023 · US
Methods and apparatus for managing register free lists
US-2023032375-A1 · Feb 2, 2023 · US
Apparatus and methods employing a shared read port register file
US-2023034072-A1 · Feb 2, 2023 · US
Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics
US-11567554-B2 · Jan 31, 2023 · US
Bit width reconfiguration using a shadow-latch configured register file
US-11544065-B2 · Jan 3, 2023 · US
Setting values of portions of registers based on bit values
US-11451241-B2 · Sep 20, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 46 |
| Ati Technologies Ulc | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30036 | 12 |
| G06F9/3867 | 10 |
| G06F9/3869 | 10 |
| G06F9/3836 | 10 |
| G06F9/384 | 9 |