Split register list for renaming

Patent metadata

Field	Value
Publication number	US-12229563-B2
Application number	US-202217855727-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jun 30, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

First claim

What is claimed is:

1. A method comprising:
detecting that a data unit size for an instruction is smaller than a pair register;
allocating a first portion of the pair register to the instruction in a manner that leaves a second portion of the pair register available for allocating to an additional instruction; and
marking the pair register as a split register using a split register list that tracks which pair registers have been split into first and second portions.

2. The method of claim 1 , wherein detecting that the data unit size for the instruction is smaller than the pair register further comprises detecting the data unit size from at least one of an instruction width and architectural signals of the instruction.

3. The method of claim 1 , wherein marking the pair register comprises setting a bit for the pair register in the split register list.

4. The method of claim 3 , wherein the split register list tracks a split register based on one of even or odd address value such that the corresponding second portion has the other of even or odd address value.

5. The method of claim 3 , further comprising unmarking, in the split register list, the pair register when the first portion and the second portion are free.

6. The method of claim 1 , further comprising selecting a first or second portion of the pair register from a free register list.

7. The method of claim 1 , further comprising marking the first portion as free when the instruction completes.

8. The method of claim 7 , further comprising marking the second portion as free when the instruction completes.

9. The method of claim 1 , further comprising marking the first and second portions as free when the instruction completes.

10. The method of claim 1 , wherein the data unit size corresponds to an instruction width of the instruction.

11. The method of claim 1 , wherein a size of the pair register corresponds to a wide instruction width.

12. The method of claim 11 , wherein a size of a register portion corresponds to half of the wide instruction width.

13. A method comprising:
detecting a data unit size from an architectural signal of an instruction;
detecting that the data unit size for the instruction is smaller than a register size;
selecting, for the instruction from a free register list, a free register having the register size;
allocating a first portion of the selected register to the instruction in a manner that leaves a second portion of the selected register available for allocating to an additional instruction; and
marking the selected register as a split register in a split register list that tracks which pair registers have been split into first and second portions.

14. The method of claim 13 , wherein the split register list tracks a split register based on one of even or odd address value such that the corresponding second portion has the other of even or odd address value.

15. The method of claim 13 , further comprising unmarking, in the split register list, the selected register when the first portion and the second portion are free.

16. The method of claim 13 , wherein free registers are each tracked in the free register list as a pair of register portions.

17. The method of claim 13 , further comprising marking the first portion as free when the instruction completes.

18. A system comprising:
a physical memory; and
at least one physical processor comprising:
a plurality of registers;
a control circuit for managing allocation of registers for instructions, the control circuit configured to:
select, for an instruction having a data unit size smaller than a register, a free register of the plurality of registers from a free register list;
allocate a first portion of the selected register to the instruction in a manner that leaves a second portion of the selected register available for allocating to an additional instruction; and
mark the selected register as a split register in a split register list that tracks which pair registers have been split into first and second portions.

19. The system of claim 18 , wherein free registers are each tracked in the free register list as a pair of register portions.

20. The system of claim 18 , wherein the first and second portions of the selected register is tracked in a free register portion list.

Assignees

• Advanced Micro Devices Inc

Inventors

• Kosuru Sree Harsha
• Dixon Eric
• Swanson Erik
• Estlick Michael
• Lowry Patrick Michael

Classifications

• G06F9/384 Primary

  Register renaming · CPC title

• G06F9/30123 Primary

  according to context, e.g. thread buffers · CPC title