Methods and apparatus for managing register free lists

Patent metadata

Field	Value
Publication number	US-11907070-B2
Application number	US-202117390293-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Jul 30, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

First claim

What is claimed is:

1. An integrated circuit comprising:
one or more processing units that execute instructions that employ a register file; and
control logic, operative to:
create a pre-startup register free list, prior to normal operation of at least one of the one or more processing units, that comprises a list of registers devoid of defective registers; and
during normal operation of the one or more processing units, employ the pre-startup register free list to select registers in the register file for executing instructions.

2. The integrated circuit of claim 1 wherein the control logic is operative to maintain, during normal operation, a register free list to only contain a plurality of registers that were on the pre-startup register free list to allocate and re-allocate registers in connection with a register file.

3. The integrated circuit of claim 1 comprising the register file configured as a repair-less register file.

4. The integrated circuit of claim 1 comprising a built-in-self-test (BIST) logic operative to detect defective registers prior to normal operation and generate a defective register list for the control logic indicating which registers of a plurality of registers are defective.

5. The integrated circuit of claim 4 wherein the control logic is operative to remove register entries from the pre-startup register free list prior to startup based on the defective register list.

6. The integrated circuit of claim 1 comprising a floating-point unit (FPU) comprising the one or more processing units and wherein the register file comprises a floating point unit register file.

7. The integrated circuit of claim 1 wherein the control logic is operative to maintain a same number of defective registers on a defective list even if a register is not defective.

8. The integrated circuit of claim 1 wherein the control logic is operative to:
create a pre-startup register free list for each of a plurality of processing units, prior to normal operation of each of the plurality of processing units, wherein each respective pre-startup register free list comprises a list of registers devoid of registers that have been detected to be defective; and
during normal operation of each of plurality of processing units, employ a respective pre-startup register free list to select registers in a respective register file for the plurality of processing units.

9. The integrated circuit of claim 1 wherein the control logic is configured to, in response to a detection of one or more registers being defective out of a plurality of registers, create a pre-startup register free list, prior to normal operation of at least one of the one or more processing units, that comprises a list of registers devoid of the one or more defective registers.

10. A method carried out by one or more processing units comprising:
create a pre-startup register free list, prior to normal operation of at least one of the one or more processing units, that comprises a list of registers devoid of defective registers; and
during normal operation of the one or more processing units, employ the pre-startup register free list to select registers in a register file for executing instructions.

11. The method of claim 10 comprising maintaining, during normal operation, a register free list to only contain a plurality of registers that were on the pre-startup register free list to allocate and re-allocate registers in connection with a register file.

12. The method of claim 10 comprising detecting, by built-in-self-test (BIST) logic defective registers prior to normal operation and generate a defective register list for control logic indicating which registers of a plurality of registers are defective.

13. The method of claim 12 comprising removing register entries from the pre-startup register free list prior to startup based on the defective register list.

14. The method of claim 10 comprising maintaining a same number of defective registers on a defective list even if a register is not defective.

15. The method of claim 10 comprising:
creating a pre-startup register free list for each of a plurality of processing units, prior to normal operation of each of the plurality of processing units, wherein each respective pre-startup register free list comprises a list of registers devoid of defective registers; and
during normal operation of each of plurality of processing units, employing a respective pre-startup register free list to select registers in a respective register file for the plurality of processing units.

16. The method of claim 10 comprising in response to a detection of one or more registers being defective out of a plurality of registers, creating a pre-startup register free list, prior to normal operation of at least one of the one or more processing units, that comprises a list of registers devoid of the one or more defective registers.

17. An integrated circuit comprising:
one or more floating point units;
a floating point unit register file, operatively coupled to the one or more floating point units;
built-in-self-test (BIST) logic operative to detect defective registers of the floating point unit register file prior to start-up of the one or more floating point units; and
control logic, operative to:
create a pre-startup register free list, prior to normal operation of at least one of the one or more floating point units, that comprises a list of registers devoid of defective registers detected by the BIST logic; and
during normal operation of the one or more floating point units, employ the pre-startup register free list to select registers in the floating point unit register file for executing instructions for the one or more floating point units.

18. The integrated circuit of claim 17 wherein the control logic is operative to maintain, during normal operation, a register free list to only contain a plurality of registers that were on the pre-startup register free list to allocate and re-allocate registers in connection with the floating point unit register file.

19. The integrated circuit of claim 17 comprising the floating point unit register file configured as a repair-less floating point unit register file.

20. The integrated circuit of claim 17 wherein the control logic is operative to remove register entries from the pre-startup register free list prior to startup based on a defective register list.

21. The integrated circuit of claim 17 wherein the control logic is operative to maintain a same number of defective registers on a defective list even if a register is not defective.

22. The integrated circuit of claim 17 wherein the control logic is operative to:
create a pre-startup register free list for each of a plurality of floating point units, prior to normal operation of each of the plurality of floating point units, wherein each respective pre-startup register free list comprises a list of registers devoid of defective registers by the BIST logic; and
during normal operation of each of the plurality of floating point units, employ a respective pre-startup register free list to select registers in a respective register file for the plurality of floating point units.

Assignees

• Advanced Micro Devices Inc

Inventors

• Busta Eric
• Golden Michael L
• O′Mullan Sean M
• Wingfield James
• Kasprak Keith A
• Schreiber Russell
• Estlick Michael

Classifications

• G06F11/1417 Primary

  Boot up procedures · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/27 Primary

  Built-in tests · CPC title