Differential pipeline delays in a coprocessor

Patent metadata

Field	Value
Publication number	US-12333309-B2
Application number	US-202318211007-A
Country	US
Kind code	B2
Filing date	Jun 16, 2023
Priority date	Dec 11, 2017
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.

First claim

What is claimed is:

1. An apparatus comprising:
a pipeline comprising a first portion and a second portion; and
a scheduler configured to cause a first subset of bits of an instruction to be provided to the first portion and a second subset of bits of the instruction to the second portion, and to tag the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline.

2. The apparatus of claim 1 , wherein a first propagation time of control signals from a controller of the pipeline to the first portion of the pipeline is less than a second propagation time of control signals from the controller to the second portion of the pipeline, and wherein the controller is configured to provide the control signals based at least in part on a difference between the first propagation time and the second propagation time.

3. The apparatus of claim 1 , wherein the scheduler is configured to cause the first subset of bits to be provided to the first portion at a first time and the second subset of bits to the second portion at a second time subsequent to the first time, and wherein the first time corresponds to a first execution cycle of the pipeline and the second time corresponds to a second execution cycle of the pipeline.

4. The apparatus of claim 3 , wherein the second execution cycle is one cycle later than the first execution cycle.

5. The apparatus of claim 4 , wherein the scheduler is configured to dispatch instructions that do not convey information between the first portion and the second portion of the pipeline on average once per cycle with a single-cycle latency.

6. The apparatus of claim 5 , wherein the scheduler is configured to dispatch instructions that convey information between the first portion and the second portion of the pipeline with a three-cycle latency.

7. The apparatus of claim 3 , wherein the first time is determined based on a first propagation time of control signals from a controller of the pipeline to the first portion of the pipeline and the second time is determined based on a second propagation time of control signals from the controller to the second portion of the pipeline.

8. The apparatus of claim 1 , wherein the first subset of bits includes a lower 128 bits of a 256-bit instruction and the second subset of bits includes an upper 128 bits of a 256-bit instruction.

9. A method comprising:
providing a first subset of bits of an instruction to a first portion of a pipeline;
providing a second subset of bits of the instruction to a second portion of the pipeline; and
tagging, by a scheduler for the pipeline, the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline.

10. The method of claim 9 , further comprising providing control signals from a controller to the first portion of the pipeline and to the second portion of the pipeline, a propagation time of the control signals from the controller to the first portion of the pipeline being less than a propagation time of the control signals from the controller to the second portion of the pipeline.

11. The method of claim 9 , wherein providing the first subset of bits includes providing the first subset of bits at a first time during a first execution cycle of the pipeline, and wherein providing the second subset of bits includes providing the second subset of bits at a second time during a second execution cycle of the pipeline.

12. The method of claim 11 , wherein providing the second subset of bits during the second execution cycle comprises providing the second subset of bits one execution cycle later than the first execution cycle.

13. The method of claim 11 , further comprising:
dispatching instructions that do not convey information between the first portion and the second portion of the pipeline on average once per execution cycle with a single-cycle latency.

14. The method of claim 11 , further comprising:
dispatching instructions that convey information between the first portion and the second portion of the pipeline with a three-cycle latency.

15. The method of claim 9 , wherein the first subset of bits includes a lower 128 bits of a 256-bit instruction and the second subset of bits includes an upper 128 bits of a 256-bit instruction.

16. A method comprising:
providing a first subset of bits of an instruction to a first portion of a pipeline;
delaying provision of a second subset of bits of the instruction to a second portion of the pipeline;
tagging the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline; and
subsequent to the delaying, providing the second subset of bits to the second portion of the pipeline.

17. The method of claim 16 , wherein providing the first subset of bits of the instruction comprises providing the first subset of bits of the instruction during a first execution cycle, and wherein delaying provision of the second subset of bits comprises delaying provision of the second subset of bits by one execution cycle.

18. The method of claim 16 , further comprising:
dispatching instructions that do not convey information between the first portion and the second portion of the pipeline on average once per cycle with a single-cycle latency; and
dispatching instructions that convey information between the first portion and the second portion of the pipeline with a three-cycle latency.

19. The method of claim 16 , wherein delaying provision of the second subset of bits comprises delaying the provision of the second subset based on a time difference between the first portion of the pipeline receiving a control signal from a controller and the second portion of the pipeline receiving the control signal from the controller.

20. The method of claim 16 , wherein the first subset of bits includes a lower 128 bits of a 256-bit instruction and the second subset of bits includes an upper 128 bits of a 256-bit instruction.

Assignees

• Advanced Micro Devices Inc

Inventors

• Fleischman Jay
• Estlick Michael
• Sedmak Michael Christopher
• Swanson Erik
• Desai Sneha V

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/3869 Primary

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title