Differential pipeline delays in a coprocessor

Patent metadata

Field	Value
Publication number	US-11709681-B2
Application number	US-201715837974-A
Country	US
Kind code	B2
Filing date	Dec 11, 2017
Priority date	Dec 11, 2017
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.

First claim

What is claimed is:

1. An apparatus comprising:
a pipeline comprising a first portion and a second portion;
a controller configured to provide control signals to the first portion of the pipeline based on a first physical distance traversed by the control signals propagating from the controller to the first portion of the pipeline being shorter than a second physical distance traversed by the control signals propagating from the controller to the second portion of the pipeline; and
a scheduler configured to cause a first subset of bits of an instruction to be provided to the first portion at a first time and a second subset of bits of the instruction to the second portion at a second time subsequent to the first time, wherein the scheduler is further configured to tag the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline.

2. The apparatus of claim 1 , wherein a propagation time of the control signals from the controller to the first portion of the pipeline is less than a propagation time of the control signals from the controller to the second portion of the pipeline.

3. The apparatus of claim 1 , wherein the first time corresponds to a first cycle of execution of the pipeline and the second time corresponds to a second cycle of execution of the pipeline.

4. The apparatus of claim 3 , wherein the second cycle is one cycle later than the first cycle.

5. The apparatus of claim 4 , wherein the scheduler is configured to dispatch instructions that do not convey information between the first portion and the second portion of the pipeline on average once per cycle with a single cycle latency.

6. The apparatus of claim 5 , wherein the scheduler is configured to dispatch instructions that convey information between the first portion and the second portion of the pipeline with a three cycle latency.

7. The apparatus of claim 1 , wherein the first subset of bits includes a lower 128 bits of a 256 bit instruction and the second subset of bits includes an upper 128 bits of a 256 bit instruction.

8. The apparatus of claim 1 , wherein the set of bits further indicates whether the first subset of the bits of the instruction is to be executed by the pipeline, and wherein the first time is determined based on a propagation time of the control signals from the controller to the first portion of the pipeline and the second time is determined based on a propagation time of the control signals from the controller to the second portion of the pipeline.

9. A method comprising:
providing, from a physical register file, a first subset of bits of an instruction to a first portion of a pipeline at a first time;
providing, from the physical register file, a second subset of bits of the instruction to a second portion of the pipeline at a second time subsequent to the first time;
tagging the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline; and
providing, from a controller, control signals to the first portion of the pipeline based on a first physical distance traversed by the control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by the control signals propagating from the controller to the second portion of the pipeline.

10. The method of claim 9 , wherein a propagation time of the control signals from the controller to the first portion of the pipeline is less than a propagation time of the control signals from the controller to the second portion of the pipeline.

11. The method of claim 9 , wherein providing the first subset of bits at the first time comprises providing the first subset of bits during a first cycle of execution of the pipeline, and wherein providing the second subset of bits at the second time comprises providing the second subset of bits during a second cycle of execution of the pipeline.

12. The method of claim 11 , wherein providing the second subset of bits during the second cycle comprises providing the second subset of bits one cycle later than the first cycle.

13. The method of claim 11 , further comprising:
dispatching instructions that do not convey information between the first portion and the second portion of the pipeline on average once per cycle with a single cycle latency.

14. The method of claim 11 , further comprising:
dispatching instructions that convey information between the first portion and the second portion of the pipeline with a three cycle latency.

15. The method of claim 9 , wherein the first subset of bits includes a lower 128 bits of a 256 bit instruction and the second subset of bits includes an upper 128 bits of a 256 bit instruction.

16. The method of claim 9 , wherein the set of bits further indicates whether the first subset of the bits of the instruction is to be executed by the pipeline.

17. A method comprising:
providing, from a physical register file, a first subset of bits of an instruction to a first portion of a pipeline;
delaying provision of a second subset of bits of the instruction from the physical register file to a second portion of the pipeline by a time interval that is determined based on a difference between a first physical distance traversed by control signals propagating from a controller to the first portion of the pipeline and a second physical distance traversed by the control signals propagating from the controller to the second portion of the pipeline; and
tagging the instruction with a set of bits that indicates whether the second subset of the bits of the instruction is to be executed by the pipeline.

18. The method of claim 17 , wherein providing the first subset of bits of the instruction comprises providing the first subset of bits of the instruction during a first cycle, and wherein delaying provision of the second subset of bits comprises delaying provision of the second subset of bits by one cycle.

19. The method of claim 17 , further comprising:
dispatching instructions that do not convey information between the first portion and the second portion of the pipeline on average once per cycle with a single cycle latency; and
dispatching instructions that convey information between the first portion and the second portion of the pipeline with a three cycle latency.

20. The method of claim 17 , wherein the set of bits further indicates whether the first subset of the bits of the instruction is to be executed by the pipeline.

Assignees

• Advanced Micro Devices Inc

Inventors

• Fleischman Jay
• Estlick Michael
• Sedmak Michael Christopher
• Swanson Erik
• Desai Sneha V

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3869 Primary

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title