Setting values of portions of registers based on bit values

Patent metadata

Field	Value
Publication number	US-11451241-B2
Application number	US-201715842027-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Dec 14, 2017
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A processor employs a set of bits to indicate values of portions of registers of a register file. In response to a specified instruction indicating an expected change of instruction types to be executed, the processor sets one or more of the bits and, for subsequent instructions, interprets corresponding portions of the registers as having a specified value (e.g., zero). By employing the set of bits to set the values of the register portions, rather than setting the individual portions of the registers to the specified value, the processor conserves processor resources (e.g., power) when the processor transitions between executing instructions of different types.

First claim

What is claimed is:

1. A method, comprising:
receiving, at a processor, a first instruction to assign a first portion of a first register a zero value, the first portion of the first register storing a first value when the first instruction is received, wherein the first value is a non-zero value;
in response to the first instruction, setting a first flag of the processor to a first state and maintaining the first value at the processor, whereby the first flag indicates that the first portion of the first register is assigned the zero value while storing the first value; and
in response to a second instruction, reading a second portion of the first register while suppressing transfer of the first portion of the first register to a memory responsive to the first flag of the processor having the first state.

2. The method of claim 1 , wherein maintaining the first value at the processor comprises maintaining the first value at the first portion of the first register.

3. The method of claim 1 , further comprising:
transferring the first value to a retire queue at an instruction pipeline of the processor.

4. The method of claim 1 , further comprising:
in response to the first instruction, setting a second flag of the processor to the first state and maintaining at the processor a second value stored at a first portion of a second register; and
in response to the second instruction, suppressing transfer of the first portion of the second register responsive to the second flag of the processor having the first state.

5. The method of claim 1 , further comprising:
in response to the second instruction, suppressing transfer of a first portion of a second register responsive to the first flag of the processor having the first state.

6. The method of claim 1 , further comprising:
in response to the first flag having the first state, setting a first portion of an architectural register of the processor to the zero value.

7. The method of claim 1 , wherein the first instruction is a VZEROUPPER instruction.

8. A method, comprising:
assigning a first architectural register of a processor to a first physical register;
receiving, at the processor, a first instruction to assign a portion of the first architectural register a zero value;
in response to the first instruction, setting a first flag of the processor to a first state and maintaining a first value at the first physical register different than the zero value, whereby the first flag indicates that the portion of the first architectural register is assigned the zero value while storing the first value; and
in response to the first flag being set, maintaining the assignment of the first architectural register to the first physical register; and
in response to a second instruction, reading a second portion of the first architectural register while suppressing transfer of the first value stored at the portion of the first architectural register to a memory.

9. The method of claim 8 , further comprising:
in response to the first instruction, transferring the first flag to a retire queue of the processor.

10. The method of claim 8 , further comprising:
in response to the first flag being set, setting portions of each of a plurality of registers to the zero value and maintaining architectural registers assigned to the plurality of registers.

11. The method of claim 8 , further comprising:
in response to the first flag being set, executing an operation at an execution unit of the processor as if the portion of the first physical register stored the zero value.

12. The method of claim 8 , wherein the first instruction is a VZEROUPPER instruction.

13. A processor, comprising:
a register file comprising a first register;
a first flag corresponding to the first register, the first flag configured to indicate if a first portion of the first register is assigned a zero value different than a non-zero value stored at the first register; and
a set of execution units configured to:
set the first flag to a first state in response to a first instruction; and
in response to a second instruction reading a second portion of the first register different than the first portion while suppressing transfer of the first portion of the first register to a memory responsive to the first flag of the processor having the first state.

14. The processor of claim 13 , wherein the set of execution units is configured to maintain a first value at the first portion of the first register in response to the first instruction.

15. The processor of claim 14 , wherein the register file is configured to transfer the first value to a retire queue at an instruction pipeline of the processor.

16. The processor of claim 13 , further comprising:
a second flag configured to indicate if a first portion of a second register contains the zero value.

17. The processor of claim 13 , further comprising:
a register rename module configured to, in response to the first flag having the first state, set a first portion of an architectural register to the zero value.

18. The processor of claim 13 , wherein the first instruction is a VZEROUPPER instruction.

Assignees

• Advanced Micro Devices Inc

Inventors

• Swanson Erik
• Desai Sneha V
• Estlick Michael

Classifications

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F16/90339

  by using parallel associative memories or content-addressable memories · CPC title

• H03M7/20 Primary

  Conversion to or from n-out-of-m codes · CPC title

• G06F16/166

  File name conversion · CPC title