Chiplet architecture for late bind SKU fungibility
US-12541476-B2 · Feb 3, 2026 · US
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Davis Mark C patents
Davis Mark C is listed as an inventor on 26 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Davis Mark C |
| Total patents | 26 |
| First publication | Mar 17, 2015 |
| Latest publication | Feb 3, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Scalable package architecture using reticle stitching and photonics for integrated circuits
US-12543594-B2 · Feb 3, 2026 · US
Rotate instructions that complete execution either without writing or reading flags
US-11900108-B2 · Feb 13, 2024 · US
Scalable package architecture using reticle stitching and photonics for zetta-scale integrated circuits
US-2023352464-A1 · Nov 2, 2023 · US
Chiplet architecture for late bind sku fungibility
US-2023305978-A1 · Sep 28, 2023 · US
Chiplet architecture chunking for uniformity across multiple chiplet configurations
US-2023305993-A1 · Sep 28, 2023 · US
Rotate instructions that complete execution either without writing or reading flags
US-2022107806-A1 · Apr 7, 2022 · US
Rotate instructions that complete execution either without writing or reading flags
US-11106461-B2 · Aug 31, 2021 · US
Multiplication instruction for which execution completes without writing a carry flag
US-10649774-B2 · May 12, 2020 · US
Source operand read suppression for graphics processors
US-10152452-B2 · Dec 11, 2018 · US
Recent patents
Latest publications not already listed above.
Rotate instructions that complete execution either without writing or reading flags
US-2018321940-A1 · Nov 8, 2018 · US
Multiplication instruction for which execution completes without writing a carry flag
US-9990201-B2 · Jun 5, 2018 · US
Multiplication instruction for which execution completes without writing a carry flag
US-2018136936-A1 · May 17, 2018 · US
Rotate instructions that complete execution either without writing or reading flags
US-9940131-B2 · Apr 10, 2018 · US
Rotate instructions that complete execution either without writing or reading flags
US-9940130-B2 · Apr 10, 2018 · US
Rotate instructions that complete execution either without writing or reading flags
US-9916160-B2 · Mar 13, 2018 · US
Task scheduling in big and little cores
US-9619282-B2 · Apr 11, 2017 · US
Systems and methods for achieving continuation of experience between components in a hybrid environment
US-9594711-B2 · Mar 14, 2017 · US
Source operand read suppression for graphics processors
US-2016350112-A1 · Dec 1, 2016 · US
Systems and methods for shared display in a hybrid environment
US-9507558-B2 · Nov 29, 2016 · US
Rotate instructions that complete execution without reading carry flag
US-9164762-B2 · Oct 20, 2015 · US
Systems and methods for communicating between components in a hybrid environment
US-9002925-B2 · Apr 7, 2015 · US
Rotate instructions that complete execution either without writing or reading flags
US-2015089201-A1 · Mar 26, 2015 · US
Rotate instructions that complete execution either without writing or reading flags
US-2015089200-A1 · Mar 26, 2015 · US
Rotate instructions that complete execution either without writing or reading flags
US-2015089199-A1 · Mar 26, 2015 · US
Task scheduling in big and little cores
US-8984200-B2 · Mar 17, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 20 |
| Davis Mark C | 6 |
| Lenovo Singapore Pte Ltd | 5 |
| Kelso Scott E | 4 |
| Cromer Daryl C | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30094 | 14 |
| G06F9/30098 | 11 |
| G06F9/30032 | 11 |
| G06F9/30014 | 3 |
| G06F9/5044 | 2 |