Task scheduling in big and little cores

Patent metadata

Field	Value
Publication number	US-9619282-B2
Application number	US-201213590467-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Aug 21, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

One aspect provides a method including: identifying a task to be scheduled for execution on an information handling device having two or more cores of different size; determining an appropriate scheduling of the task for execution on the two or more of cores of different size, wherein the appropriate scheduling of the task is determined via a core signature for the task; directing the task to an appropriate core for execution based on the appropriate scheduling determined; and executing the task on the appropriate core. Other aspects are described and claimed.

First claim

What is claimed is:

1. A method comprising:
identifying a task to be scheduled for execution on an information handling device having two or more cores of different size;
determining an appropriate scheduling of the task for execution on the two or more of cores of different size, wherein the appropriate scheduling of the task is determined via a core signature for the task, wherein the core signature is determined via a procedure comprising: determining if the task fits on a little core; determining if the task is high priority; and determining if the task is executable on the little core within a threshold tolerance with respect to little core utilization;
directing the task to an appropriate core for execution based on the appropriate scheduling determined; and
executing the task on the appropriate core.

2. The method of claim 1 , wherein a big core of the cores of different size is a high power central processing unit, and further wherein a little core of the cores of different size is a lower power central processing unit with respect to the big core.

3. The method of claim 1 , wherein the core signature comprises a tracked execution history.

4. The method of claim 1 , wherein the core signature comprises an ascertained task characteristic.

5. The method of claim 4 , wherein the ascertained task characteristic comprises a characteristic indicating that the task is a high priority task.

6. The method of claim 1 , wherein the core signature is programmed for the task and comprises a hint associated with the entire task.

7. The method of claim 1 , wherein the core signature is programmed for the task and comprises a hint associated with a sub-component of the task.

8. The method of claim 1 , wherein the core signature is programmed for the task and is static.

9. The method of claim 1 , wherein the core signature is programmed for the task and is dynamically updated during execution of the task.

10. An information handling device, comprising:
one or more processors; and
a memory in communication with the one or more processors;
the memory storing program instructions that when executed by the one or more processors:
identify a task to be scheduled for execution on an information handling device having two or more cores of different size;
determine an appropriate scheduling of the task for execution on the two or more of cores of different size, wherein the appropriate scheduling of the task is determined via a core signature for the task, wherein the core signature is determined via a procedure comprising: determining if the task fits on a little core; determining if the task is high priority; and determining if the task is executable on the little core within a threshold tolerance with respect to little core utilization;
direct the task to an appropriate core for execution based on the appropriate scheduling determined; and
execute the task on the appropriate core.

11. The information handling device of claim 10 , wherein a big core of the cores of different size is a high power central processing unit, and further wherein a little core of the cores of different size is a lower power central processing unit with respect to the big core.

12. The information handling device of claim 10 , wherein the core signature comprises a tracked execution history.

13. The information handling device of claim 10 , wherein the core signature comprises an ascertained task characteristic.

14. The information handling device of claim 13 , wherein the ascertained task characteristic comprises a characteristic indicating that the task is a high priority task.

15. The information handling device of claim 10 , wherein the core signature is programmed for the task and comprises a hint associated with the entire task.

16. The information handling device of claim 10 , wherein the core signature is programmed for the task and comprises a hint associated with a sub-component of the task.

17. The information handling device of claim 10 , wherein the core signature is programmed for the task and is static.

18. The information handling device of claim 10 , wherein the core signature is programmed for the task and is dynamically updated during execution of the task.

19. A program product, comprising:
a storage device having program code embodied therewith, the program code comprising:
program code configured to identify a task to be scheduled for execution on an information handling device having two or more cores of different size;
program code configured to determine an appropriate scheduling of the task for execution on the two or more of cores of different size, wherein the appropriate scheduling of the task is determined via a core signature for the task, wherein the core signature is determined via a procedure comprising: determining if the task fits on a little core; determining if the task is high priority; and determining if the task is executable on the little core within a threshold tolerance with respect to little core utilization;
program code configured to direct the task to an appropriate core for execution based on the appropriate scheduling determined; and
program code configured to execute the task on the appropriate core.

Assignees

• Davis Mark C
• Cromer Daryl C
• Locker Howard J
• Kelso Scott E
• Lenovo Singapore Pte Ltd

Inventors

• Davis Mark C
• Cromer Daryl C
• Locker Howard J
• Kelso Scott E

Classifications

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/4887

  involving deadlines, e.g. rate based, periodic · CPC title

• G06F2209/5021

  Priority · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title