Source operand read suppression for graphics processors

Patent metadata

Field	Value
Publication number	US-10152452-B2
Application number	US-201514726349-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Techniques to suppress redundant reads to register addresses and to replicate read data are disclosed. The redundant reads are suppressed when multiple source operands specify the same register address to read. Additionally, the read data is replicated to a data stream or data location corresponding to the source operands where the data read was suppressed.

First claim

What is claimed is:

1. An apparatus, comprising:
circuitry to execute an instruction, the instruction to include an indication of at least a first source operand and a second source operand, the first source operand corresponding to a first register address and the second source operand corresponding to a second register address; and
redundant read suppression (RRS) logic, the RRS logic to:
determine whether the first register address is the same as the second register address by comparison of the second register address with register addresses of other source operands in the instruction;
suppress a read to the second register address based on the determination that the first register address is the same as the second register address; and
replicate data read from the first register address to a data stream corresponding to the second source operand based on suppression of the read to the second register address.

2. The apparatus of claim 1 , the instruction to include an indication of a third source operand, the third source operand corresponding to a third register address, the RRS logic to:
determine whether the first register address is the same as the third register address; and
based on a determination that the first register address is the same as the third register address:
suppress a read to the third register; and

replicate data read from the first register address to a data stream corresponding to the third source operand.

3. The apparatus of claim 2 , the RRS logic to:
determine whether the second register address is the same as the third register address; and
suppress a read to the third register address based on a determination that the second register address is the same as the third register address.

4. The apparatus of claim 3 , the RRS logic to replicate data read from the second register address to a data stream corresponding to the third source operand based on the determination that the second register address is the same as the third register address.

5. The apparatus of claim 1 , the instruction a first instruction, the circuitry to execute a second instruction, the second instruction to include an indication of at least a third source operand and a fourth source operand, the third source operand corresponding to a third register address and the fourth source operand corresponding to a fourth register address, the RRS logic to:
determine whether the first register address is the same as the third register address;
suppress a read to the third register address based on a determination that the first register address is the same as the third register address;
determine whether the first register address is the same as the fourth register address; and
suppress a read to the fourth register address based on a determination that the first register address is the same as the fourth register address.

6. The apparatus of claim 5 , the RRS logic to:
replicate data read from the first register address to a data stream corresponding to the third source operand based on the determination that the first register address is the same as the third register address; and
replicate data read from the first register address to a data stream corresponding to the fourth source operand based on the determination that the first register address is the same as the fourth register address.

7. The apparatus of claim 5 , the RRS logic to:
determine whether the second register address is the same as the third register address;
suppress a read to the third register address based on a determination that the second register address is the same as the third register address;
determine whether the second register address is the same as the fourth register address; and
suppress a read to the fourth register address based on a determination that the second register address is the same as the fourth register address.

8. The apparatus of claim 7 , the RRS logic to:
replicate data read from the second register address to a data stream corresponding to the third source operand based on the determination that the second register address is the same as the third register address; and
replicate data read from the second register address to a data stream corresponding to the fourth source operand based on the determination that the second register address is the same as the fourth register address.

9. The apparatus of claim 5 , the RRS logic to:
determine whether the third register address is the same as the fourth register address;
suppress a read to the fourth register address based on a determination that the third register address is the same as the fourth register address; and
replicate data read from the third register address to a data stream corresponding to the fourth source operand based on the determination that the third register address is the same as the fourth register address.

10. The apparatus of claim 1 , the circuitry and the RRS logic comprising a graphics processing unit.

11. The apparatus of claim 1 , comprising a display operably coupled to the circuitry to display data processed by the circuitry.

12. The apparatus of claim 1 , comprising a wireless radio operably coupled to the circuitry to receive data to be processed by the circuitry.

13. A computer-implemented method comprising:
executing, by a graphics processing unit, an instruction, the instruction to include an indication of at least a first source operand and a second source operand, the first source operand corresponding to a first register address and the second source operand corresponding to a second register address;
determining whether the first register address is the same as the second register address by comparison of the second register address with register addresses of other source operands in the instruction;
suppressing a read to the second register address based on the determination that the first register address is the same as the second register address;
replicating data read from the first register address to a data stream corresponding to the second source operand based on suppression of the read to the second register address.

14. The computer-implemented method of claim 13 , the instruction to include an indication of a third source operand, the third source operand corresponding to a third register address, the method comprising:
determining whether the first register address is the same as the third register address; and
based on a determination that the first register address is the same as the third register address:
suppressing a read to the third register address; and
replicating data read from the first register address to a data stream corresponding to the third source operand.

15. The computer-implemented method of claim 14 , comprising:
determining whether the second register address is the same as the third register address; and
suppressing a read to the third register address based on a determination that the second register address is the same as the third register address.

16. The computer-implemented method of claim 15 , comprising replicating data read from the second register address to a data stream corresponding to the third source operand based on the determination that the second register address is the same as the third register address.

17. The computer-implemented method of claim 13 , the instruction a first instruction, the method comprising:
executing, by the graphics processing unit, a second instruction, the second instruction to include an indication of at least a third source operand and a fourth source operan

Assignees

• Intel Corp

Inventors

• Pal Supratim
• Maiyuran Subramaniam
• Davis Mark C

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F15/82 Primary

  data or demand driven · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/30141 Primary

  Implementation provisions of register files, e.g. ports · CPC title