Rotate instructions that complete execution either without writing or reading flags

Patent metadata

Field	Value
Publication number	US-9940131-B2
Application number	US-201414562310-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Dec 26, 2009
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

First claim

What is claimed is:

1. A cell phone comprising:
a random access memory (RAM);
a wireless transceiver; and
a multi-core processor comprising:
at least four cores, wherein each of the at least four cores comprises:
at least one level 1 (L1) cache;
a register to store a plurality of flags, including a carry flag, a sign flag, a zero flag, and an overflow flag;
at least sixteen 64-bit general-purpose registers, wherein the 64-bit general-purpose registers are operable to store 64-bit operands in a 64-bit mode and are operable to store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are to be stored in a lower 32-bits of the 64-bit general-purpose registers;
a branch prediction logic;
an instruction fetch logic to fetch a rotate right instruction;
a decoder to decode the rotate right instruction, wherein the rotate right instruction is to indicate a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and is to have a field to specify a first 64-bit general-purpose register; and
a plurality of execution units, including a first execution unit to execute the rotate right instruction, wherein the rotate right instruction is to cause the first execution unit to rotate the first 64-bit source operand right by an amount that is to be indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are to be rotated into a most significant bit of the first 64-bit source operand, and to store a result that is to include the first 64-bit source operand rotated right by the amount into the first 64-bit general-purpose register, and wherein the rotate right instruction is to complete without causing the carry flag to be read, without causing the carry flag to be written, without causing the sign flag to be written, without causing the zero flag to be written, and without causing the overflow flag to be written.

2. The cell phone of claim 1 , wherein the processor further comprises a shared level 2 (L2) cache that is to be shared by the at least four cores, and wherein the random access memory is to store a cryptographic algorithm that is to use the rotate right instruction.

3. The cell phone of claim 1 , wherein the processor comprises a reduced instruction set computing (RISC) processor.

4. The cell phone of claim 1 , wherein the rotate right instruction has at least one bit to specify the 64-bit operand size.

5. The cell phone of claim 1 , wherein the rotate right instruction is to complete without causing any arithmetic flags to be read and without causing said any arithmetic flags to be written.

6. The cell phone of claim 1 , wherein the rotate right instruction is to complete without causing any flags to be read. written.

7. A cell phone comprising:
a random access memory (RAM);
a wireless transceiver; and
a multi-core processor comprising:
at least four cores, wherein each of the at least four cores comprises:
at least one level 1 (L1) cache;
a register to store a plurality of flags, including a carry flag, a sign flag, a zero flag, and an overflow flag;
at least sixteen 64-bit general-purpose registers, wherein the 64-bit general-purpose registers are operable to store 64-bit operands in a 64-bit mode and are operable to store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are to be stored in a lower 32-bits of the 64-bit general-purpose registers;
a branch prediction logic;
an instruction fetch logic to fetch a rotate right instruction;
a decoder to decode the rotate right instruction, wherein the rotate right instruction is to indicate a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and is to have a field to specify a first 64-bit general-purpose register; and
a plurality of execution units, including a first execution unit to execute the rotate right instruction, wherein the rotate right instruction is to cause the first execution unit to rotate the first 64-bit source operand right by an amount that is to be indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are to be rotated into a most significant bit of the first 64-bit source operand, and to store the first 64-bit source operand rotated right by the amount as a result into the first 64-bit general-purpose register, and wherein the rotate right instruction is to complete without causing the carry flag to be read, without causing the sign flag to be read, without causing the zero flag to be read, and without causing the overflow flag to be read.

8. The cell phone of claim 7 , wherein the processor comprises a reduced instruction set computing (RISC) processor.

9. The cell phone of claim 7 , wherein the processor further comprises a shared level 2 (L2) cache that is to be shared by the at least four cores.

10. The cell phone of claim 7 , wherein the rotate right instruction has at least one bit to specify the 64-bit operand size.

11. The cell phone of claim 7 , wherein the rotate right instruction is to complete without causing any flags to be written, and wherein the random access memory is to store a cryptographic algorithm that is to use the rotate right instruction.

12. A cell phone comprising:
a random access memory (RAM);
a wireless transceiver; and
a multi-core processor comprising:
at least four cores, wherein each of the at least four cores comprises:
at least one level 1 (L1) cache;
a register to store a plurality of flags, including a carry flag, a sign flag, a zero flag, and an overflow flag;
at least sixteen 64-bit general-purpose registers, wherein the 64-bit general-purpose registers are operable to store 64-bit operands in a 64-bit mode and are operable to store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are to be stored in a lower 32-bits of the 64 general-purpose registers;
a branch prediction logic;
an instruction fetch logic to fetch a first rotate right instruction;
a decoder to decode the first rotate right instruction and a second rotate right instruction, wherein the first rotate right instruction is to indicate a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and is to have a field to specify a first 64-bit general-purpose register; and
a plurality of execution units, including a first execution unit to execute the first rotate right instruction, wherein the first rotate right instruction is to cause the first execution unit to rotate the first 64-bit source operand right by an amount that is to be indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are to be rotated into a most significant bit of the first 64-bit source operand, and to store a result that is to include the first 64-bit source operand rotated by the amount into the first 64-bit general-purpose register, and wherein the first rotate right instruction is to complete without causing the carry flag to be read, without causing the carry flag to be written, without causing the sign flag to be written, without causing the zero flag to be written, and without causing the overflow flag to be written, and wherein the second rotate right instruction when executed is to cause the carry flag to be read.

13. The cell phone of claim 12 , wherein the rotated first 64-bit source operand is to be stored as the result.

14. The cell phone of claim 12 , wherein the processor further comprises a shared level 2 (L2) cache that is to be shared by the at least four cores, and wherein the random access memor

Assignees

• Intel Corp

Inventors

• Gopal Vinodh
• Guilford James D
• Wolrich Gilbert M
• Feghali Wajdi K
• Ozturk Erdinc
• Dixon Martin G
• Mirkes Sean
• Toll Bret L
• Loktyukhin Maxim
• Davis Mark C
• Farcy Alexandre J

Classifications

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title