Multiplication instruction for which execution completes without writing a carry flag

Patent metadata

Field	Value
Publication number	US-9990201-B2
Application number	US-64538309-A
Country	US
Kind code	B2
Filing date	Dec 22, 2009
Priority date	Dec 22, 2009
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

First claim

What is claimed is:

1. A method comprising:
receiving a multiply instruction, the multiply instruction indicating source operands consisting of only a first source operand and a second source operand, wherein the first and second source operands have a same size;
performing a multiply operation, including propagating carries, on the first and second source operands to generate a product of the first and second source operands; and
storing a product of the first and second source operands in one or more destination operands indicated by the multiply instruction, wherein the one or more destination operands in which the product is stored have twice as many bits as each of the first and second source operands; and
completing execution of the multiply instruction without writing a carry flag,
wherein the multiply instruction is included in an instruction set with another multiply instruction that when performed is to cause updating of the carry flag dependent upon a corresponding product.

2. The method of claim 1 , wherein completing comprises completing execution of the multiply instruction without writing the carry flag regardless of a value of the product.

3. The method of claim 1 , wherein completing comprises completing execution of the multiply instruction without reading the carry flag.

4. The method of claim 1 , wherein completing comprises completing execution of the multiply instruction without reading or writing an overflow flag.

5. The method of claim 1 , wherein receiving comprises receiving the multiply instruction that explicitly specifies a first destination operand of the one or more destination operands and implicitly indicates a second destination operand of the one or more destination operands.

6. The method of claim 1 , wherein receiving comprises receiving the multiply instruction that implicitly indicates but does not explicitly specify a source operand selected from the first and second source operands and that implicitly indicates but does not explicitly specify a destination operand of the one or more destination operands, and wherein the implicitly indicated source operand corresponds to a different storage location than the implicitly indicated destination operand.

7. The method of claim 1 , further comprising:
receiving a second multiply instruction indicating a third source operand and a fourth source operand; storing a second product of the third and fourth source operands in one or more second destination operands indicated by the second multiply instruction; and completing execution of the second multiply instruction without writing the carry flag; and
adding the product and the second product utilizing the carry flag.

8. The method of claim 1 , wherein the size of each of the first and second source operands is one of 32 bits and 64 bits, wherein the first source operand comprises a location in a general purpose register, and wherein the product comprises a product of unsigned integers, and wherein the one or more destination operands comprise two destination operands each of a same size as the size of each of the first and second source operands.

9. The method of claim 1 , wherein the method is performed by a general-purpose microprocessor having a plurality of cores, and wherein at least one of the cores has circuitry responsive to the instruction and is also operable to execute a second multiply instruction that indicates third and fourth source operands of a same size to generate a second product of the third and fourth source operands indicated by the second multiply instruction and write the carry flag depending on a value of the second product.

10. The method of claim 1 , further comprising decoding an ADD instruction, an ADC instruction, and a MOV instruction, and wherein the carry flag is in an EFLAGS register.

11. An apparatus comprising:
a register to store a carry flag; and
an execution unit coupled with the register and that is operable as a result of a multiply instruction that is to indicate source operands consisting of only a first source operand and a second source operand that are each to have a same size to multiply the first and second source operands with carry propagation to generate a product and to store the product of the first and second source operands in one or more destination operands that are to be indicated by the multiply instruction, the one or more destination operands to have twice as many bits as each of the first and second source operands, and the execution unit to complete execution of the multiply instruction without writing the carry flag, wherein the multiply instruction is part of an instruction set that also includes another multiply instruction that is to be performed to generate a product and update the carry flag dependent upon a value of the product of said another multiplication instruction.

12. The apparatus of claim 11 , wherein the execution unit is to complete execution of the multiply instruction without writing the carry flag regardless of a value of the product.

13. The apparatus of claim 11 , wherein the execution unit is to complete execution of the multiply instruction without reading the carry flag.

14. The apparatus of claim 11 , wherein the execution unit is to complete execution of the multiply instruction without reading or writing an overflow flag.

15. The apparatus of claim 11 , wherein the execution unit is operable to store at least part of the product at a first destination operand of the one or more destination operands that is to be explicitly specified by the multiply instruction and at least part of the product at a second destination operand of the one or more destination operands that is to be implicitly indicated by the multiply instruction.

16. The apparatus of claim 15 , wherein the execution unit is operable to store highest order bits of the product at the explicitly specified first destination operand, and wherein the execution unit is operable to store lowest order bits of the product at the implicitly indicated second destination operand.

17. The apparatus of claim 11 , wherein the execution unit is operable to receive a source operand that is one of the first and second source operands that is to be implicitly indicated by the multiply instruction, wherein the execution unit is operable to store at least part of the product at a destination operand of the one or more destination operands that is to be implicitly indicated by the multiply instruction, and wherein the implicitly indicated source operand is to correspond to a different storage location than the implicitly indicated destination operand.

18. The apparatus of claim 17 , wherein the storage location corresponding to the implicitly indicated source operand comprises a general-purpose register that is one of a 32-bit register and a 64-bit register, and wherein the storage location corresponding to the implicitly indicated destination operand comprises a general-purpose register that is one of a different 32-bit register and a different 64-bit register.

19. The apparatus of claim 11 , wherein the product comprises a product of unsigned integers, and further comprising first and second general-purpose registers to respectively store the first and second source operands, wherein the first and second general-purpose registers each have the same size and that size is one of 32-bits and 64-bits.

20. The apparatus of claim 11 , wherein the instruction comprises a machine instruction, wherein the execution unit comprises circuitry responsive to the machine ins

Assignees

• Gopal Vinodh
• Guilford James D
• Feghali Wajdi K
• Ozturk Erdine
• Wolrich Gilbert M
• Dixon Martin G
• Davis Mark C
• Mirkes Sean P
• Farcy Alexandre
• Toll Bret L
• Loktyukhin Maxim
• Intel Corp

Inventors

• Gopal Vinodh
• Guilford James D
• Feghali Wajdi K
• Ozturk Erdine
• Wolrich Gilbert M
• Dixon Martin G
• Davis Mark C
• Mirkes Sean P
• Farcy Alexandre
• Toll Bret L
• Loktyukhin Maxim

Classifications

• G06F9/30094 Primary

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/30014

  with variable precision · CPC title