Scalable package architecture using reticle stitching and photonics for integrated circuits

Patent metadata

Field	Value
Publication number	US-12543594-B2
Application number	US-202217733880-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Apr 29, 2022
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits. One or more of the second IC dies comprises a second circuit different from the first circuit, adjacent ones of the first circuits are coupled by a conductive pathway through the corresponding scribe regions, and the first IC die and the second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.

First claim

The invention claimed is:

1 . A microelectronic assembly, comprising:
a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions between adjacent ones of the plurality of first circuits; and a plurality of second IC dies coupled to the first IC die, each one of the plurality of second IC dies being coupled proximate and adjacent to a corresponding one of the plurality of first circuits and conductively coupled to the corresponding one of the plurality of first circuits, wherein:
one or more of the plurality of second IC dies comprises a second circuit different from the plurality of first circuits,
adjacent ones of the plurality of first circuits are coupled by a conductive pathway through the scribe regions, and
the first IC die and the plurality of second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.

2 . The microelectronic assembly of claim 1 , wherein each of the scribe regions comprises at least one of alignment marks, metal structures conductively uncoupled from the plurality of first circuits, and a region without the metal structures.

3 . The microelectronic assembly of claim 1 , wherein:
the plurality of first circuits are dynamic random-access memory (DRAM) circuits, and the second circuit is at least one of a physical layer interface (PHY) circuit or a network circuit.

4 . The microelectronic assembly of claim 1 , wherein the first IC die comprises a stack of first IC dies coupled by an interconnect layer having interconnects at a pitch not more than 10 micrometers between adjacent ones of the interconnects.

5 . The microelectronic assembly of claim 1 , further comprising a plurality of third IC dies, wherein:
subsets of the plurality of third IC dies are coupled to corresponding ones of the plurality of second IC dies on a side of the plurality of second IC dies opposite to the first IC die, and subsets of the plurality of third IC dies are coupled to corresponding ones of the plurality of second IC dies by interconnects having a pitch not more than 10 micrometers between adjacent ones of the interconnects.

6 . The microelectronic assembly of claim 5 , wherein at least one IC die in the plurality of third IC dies comprises a digital logic circuits.

7 . The microelectronic assembly of claim 5 , wherein at least one IC die in the plurality of third IC dies comprises a cache-memory circuits.

8 . The microelectronic assembly of claim 1 , further comprising a photonics IC die (PIC) coupled to one or more of the plurality of second IC dies in the plurality of second IC dies on a side of the plurality of second IC dies opposite to the first IC die, wherein the PIC is coupled to the plurality of second IC dies by interconnects having a pitch not more than 10 micrometers between adjacent ones of the interconnects.

9 . An IC package, comprising:
a first IC die comprising a plurality of memory circuits and a plurality of scribe regions, each of the plurality of scribe regions between adjacent ones of the plurality of memory circuits; a plurality of second IC dies coupled to the first IC die, each one of plurality of the second IC dies proximate to and conductively coupled to a corresponding one of the plurality of memory circuits; and a plurality of third IC dies, distinct subsets of the plurality of third IC dies being coupled to separate ones of the plurality of second IC dies on sides of the plurality of second IC dies opposite to the first IC die, wherein: each subset of the plurality of third IC dies is conductively coupled together by a network circuit in the plurality of second IC die to which the subset is coupled, and adjacent ones of the plurality of memory circuits are conductively coupled by conductive pathways through the plurality of scribe regions.

10 . The IC package of claim 9 , further comprising at least one PIC coupled to at least one of the plurality of second IC dies, wherein the at least one PIC is configured to couple to an optical fiber for enabling communication between the IC package and another IC package.

11 . The IC package of claim 10 , wherein the plurality of second IC dies is conductively coupled to the at least one PIC.

12 . The IC package of claim 9 , wherein the first IC die comprises a plurality of stacked monolithic wafers coupled by interconnects having a pitch not more than 10 micrometers between adjacent ones of the interconnects.

13 . The IC package of claim 12 , wherein each of plurality of stacked monolithic wafers comprises a plurality of memory circuits and a plurality of scribe regions, the plurality of scribe regions being between adjacent ones of the plurality of memory circuits.

14 . The IC package of claim 9 , further comprising a package substrate.

15 . The IC package of claim 14 , wherein the first IC die is coupled to the package substrate on a side of the first IC die opposite to the plurality of second IC dies.

16 . A method, comprising:
providing a first IC die including a first circuit, a second circuit and a scribe region between the first circuit and the second circuit; providing a second IC die comprising a third circuit different from the first circuit or the second circuit; and coupling the second IC die to the first IC die proximate to the first circuit and distant from the second circuit by interconnects having a pitch not more than 10 micrometers between adjacent interconnects, wherein:
at least one of the first circuit and the second circuit is approximately 700 square millimeters in area, and
the first circuit and the second circuit are coupled by a conductive pathway through the scribe region.

17 . The method of claim 16 , further comprising coupling a PIC to the second IC die.

18 . The method of claim 17 , further comprising coupling the PIC to an optical fiber.

19 . The method of claim 16 , further comprising coupling a plurality of third IC dies to the second IC die opposite to the first IC die, wherein the plurality of third IC dies comprises separate fourth circuits different from the first circuit, the second circuit, or the third circuit.

20 . The method of claim 19 , further comprising coupling the separate fourth circuits in the plurality of third IC dies by the third circuit in the second IC die.

Assignees

• Intel Corp

Inventors

• Damaraju Satish
• Siers Scott E
• Kokar Altug
• Gomes Wilfred
• Davis Mark C

Classifications

• H01L2924/1436

  Electricity · mapped topic

• H01L2924/1431

  Electricity · mapped topic

• H01L2224/80896

  Electricity · mapped topic

• H01L2224/80895

  Electricity · mapped topic

• H01L2224/16238

  Electricity · mapped topic