Clear prefetch stream on detection of pipeline flush
US-2025130947-A1 · Apr 24, 2025 · US
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Britto Vivek patents
Britto Vivek is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Britto Vivek |
| Total patents | 27 |
| First publication | Mar 12, 2020 |
| Latest publication | Apr 24, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Method for latency detection on a hardware simulation accelerator
US-11875095-B2 · Jan 16, 2024 · US
Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers
US-11645208-B2 · May 9, 2023 · US
Detecting deviations from targeted design performance in accelerator/emulator environment
US-11562116-B2 · Jan 24, 2023 · US
Prefetch store preallocation in an effective address-based cache directory
US-11520585-B2 · Dec 6, 2022 · US
Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers
US-2022309001-A1 · Sep 29, 2022 · US
Reducing the memory load time for logic simulator by leveraging architecture simulator
US-11321225-B2 · May 3, 2022 · US
Dynamically adjusting prefetch depth
US-11301386-B2 · Apr 12, 2022 · US
Detecting deviations from targeted design performance in accelerator/emulator environment
US-2022012393-A1 · Jan 13, 2022 · US
Method for latency detection on a hardware simulation accelerator
US-2022004680-A1 · Jan 6, 2022 · US
Recent patents
Latest publications not already listed above.
Reducing the memory load time for logic simulator by leveraging architecture simulator
US-2021365294-A1 · Nov 25, 2021 · US
Prefetch store preallocation in an effective address-based cache directory
US-2021342268-A1 · Nov 4, 2021 · US
Dynamically adjusting prefetch depth
US-11163683-B2 · Nov 2, 2021 · US
Dynamic modification of instructions that do not modify the architectural state of a processor
US-11157285-B2 · Oct 26, 2021 · US
Performance benchmark generation
US-11138089-B2 · Oct 5, 2021 · US
Prefetch queue allocation protection bubble in a processor
US-11093248-B2 · Aug 17, 2021 · US
Dynamic modification of instructions that do not modify the architectural state of a processor
US-2021247982-A1 · Aug 12, 2021 · US
Processor prefetcher mode governor for switching between prefetch modes
US-10963249-B2 · Mar 30, 2021 · US
Dynamically adjusting prefetch depth
US-2021034528-A1 · Feb 4, 2021 · US
Dynamically adjusting prefetch depth
US-2021034529-A1 · Feb 4, 2021 · US
Software translation prefetch instructions
US-10754791-B2 · Aug 25, 2020 · US
Software translation prefetch instructions
US-2020210346-A1 · Jul 2, 2020 · US
Performance benchmark generation
US-2020201739-A1 · Jun 25, 2020 · US
Prefetch stream allocation for multithreading systems
US-10671394-B2 · Jun 2, 2020 · US
Processor prefetcher mode governor for switching between prefetch modes
US-2020142698-A1 · May 7, 2020 · US
Prefetch stream allocation for multithreading systems
US-2020133671-A1 · Apr 30, 2020 · US
Prefetch Queue Allocation Protection Bubble in a Processor
US-2020081714-A1 · Mar 12, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 27 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0862 | 17 |
| G06F2212/1024 | 8 |
| G06F2212/602 | 8 |
| G06F2212/6028 | 7 |
| G06F12/0811 | 6 |