Software translation prefetch instructions

Patent metadata

Field	Value
Publication number	US-10754791-B2
Application number	US-201916237780-A
Country	US
Kind code	B2
Filing date	Jan 2, 2019
Priority date	Jan 2, 2019
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.

First claim

What is claimed is:

1. A system, comprising a processor configured to:
based on encountering a translation prefetch instruction in software that is being executed by the processor:
determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor;
based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction; and
storing an address translation corresponding to the address translation request in the TLB;
wherein the translation prefetch instruction is located before a data prefetch instruction in the software, and wherein the data prefetch instruction uses the address translation corresponding to the translation prefetch instruction in the TLB.

2. The system of claim 1 , wherein the translation prefetch instruction corresponds to an instruction set architecture (ISA) of the processor.

3. The system of claim 1 , the processor configured to:
based on determining that the address translation is not located in the TLB, reserve an entry corresponding to the translation prefetch instruction in a translation miss queue.

4. The system of claim 3 , the processor configured to:
based on reserving the entry corresponding to the translation prefetch instruction in the translation miss queue, retire the translation prefetch instruction in a pipeline of the processor.

5. The system of claim 3 , the processor configured to:
based on storing the address translation corresponding to the address translation request in the TLB, release the entry corresponding to the translation prefetch instruction in the translation miss queue.

6. The system of claim 1 , wherein the translation prefetch instruction comprises a virtual memory address, and wherein the address translation comprises a real memory address.

7. A computer-implemented method, comprising:
based on encountering a translation prefetch instruction in software that is being executed by a processor:
determining, by the processor, whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor;
based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction; and
storing an address translation corresponding to the address translation request in the TLB;
wherein the translation prefetch instruction is located before a data prefetch instruction in the software, and wherein the data prefetch instruction uses the address translation corresponding to the translation prefetch instruction in the TLB.

8. The computer-implemented method of claim 7 , wherein the translation prefetch instruction corresponds to an instruction set architecture (ISA) of the processor.

9. The computer-implemented method of claim 7 , further comprising:
based on determining that the address translation is not located in the TLB, reserve an entry corresponding to the translation prefetch instruction in a translation miss queue.

10. The computer-implemented method of claim 9 , further comprising:
based on reserving the entry corresponding to the translation prefetch instruction in the translation miss queue, retire the translation prefetch instruction in a pipeline of the processor.

11. The computer-implemented method of claim 9 , further comprising:
based on storing the address translation corresponding to the address translation request in the TLB, release the entry corresponding to the translation prefetch instruction in the translation miss queue.

12. The computer-implemented method of claim 7 , wherein the translation prefetch instruction comprises a virtual memory address, and wherein the address translation comprises a real memory address.

13. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
based on encountering a translation prefetch instruction in software that is being executed by a processor:
determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor;
based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction; and
storing an address translation corresponding to the address translation request in the TLB;
wherein the translation prefetch instruction is located before a data prefetch instruction in the software, and wherein the data prefetch instruction uses the address translation corresponding to the translation prefetch instruction in the TLB.

14. The computer program product of claim 13 , wherein the translation prefetch instruction corresponds to an instruction set architecture (ISA) of the processor.

15. The computer program product of claim 13 , further comprising:
based on determining that the address translation is not located in the TLB, reserve an entry corresponding to the translation prefetch instruction in a translation miss queue.

16. The computer program product of claim 15 , further comprising:
based on reserving the entry corresponding to the translation prefetch instruction in the translation miss queue, retire the translation prefetch instruction in a pipeline of the processor.

17. The computer program product of claim 15 , further comprising:
based on storing the address translation corresponding to the address translation request in the TLB, release the entry corresponding to the translation prefetch instruction in the translation miss queue.

18. The computer program product of claim 13 , wherein the translation prefetch instruction comprises a virtual memory address, and wherein the address translation comprises a real memory address.

Assignees

• IBM

Inventors

• Britto Vivek
• Cockcroft Bryant
• Schumann John
• Pindicura Tharunachalam
• Srivatsan Shricharan
• Xia Yan
• Dhandapani Aishwarya

Classifications

• G06F12/0862

  with prefetch · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/654

  Look-ahead translation · CPC title

• G06F2212/507

  using speculative control · CPC title