Detecting deviations from targeted design performance in accelerator/emulator environment

Patent metadata

Field	Value
Publication number	US-11562116-B2
Application number	US-202016922514-A
Country	US
Kind code	B2
Filing date	Jul 7, 2020
Priority date	Jul 7, 2020
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

First claim

The invention claimed is:

1. A method comprising:
loading a list of target values for a performance metric onto a hardware-accelerated simulator;
setting breakpoints to pause the hardware-accelerated simulator at defined intervals;
simulating, by the hardware-accelerated simulator, execution of a circuit design including collecting a checkpoint of the execution of the circuit design at a start of each defined interval;
during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric;
deleting, in response to the difference between the measured value for the performance metric and the target value for the performance value is within a preset tolerance, the collected checkpoint; and
ending the simulation when a specified condition based on said comparing is met.

2. The method according to claim 1 , wherein:
the comparing a measured value for the performance metric to the target value for the performance metric includes
at an end of each of the intervals, comparing the measured value for the performance metric to the target value for the performance metric, and
when the difference between the measured value for the performance metric and the target value for the performance metric is within the preset tolerance, ending the each pause and continuing the simulating execution of the circuit design.

3. The method according to claim 1 , wherein the comparing a measured value for the performance metric to the target value for the performance metric further includes:
when the difference between the measured value for the performance metric and the target value for the performance metric is outside the preset tolerance,
incrementing a count,
comparing the incremented count to a preset limit, and
when the incremented count does not exceed the preset limit, ending the each pause and continuing the simulating execution of the circuit design.

4. The method according to claim 3 , wherein the ending the simulation when a specified condition based on said comparing is met includes ending the simulation when the incremented count exceeds the preset limit.

5. The method according to claim 3 , wherein the simulating, by the hardware-accelerated simulator, execution of a circuit design further includes when the difference between the measured value for the performance metric and the target value for the performance metric is outside the preset tolerance, saving the collected checkpoint.

6. The method according to claim 5 , wherein the incrementing a count includes keeping track of a number of the saved checkpoints.

7. The method according to claim 6 , wherein the ending the simulation when a specified condition based on said comparing is met includes ending the simulation when the number of the saved checkpoints exceeds the preset limit.

8. The method according to claim 1 , wherein the comparing a measured value for the performance metric to the target value for the performance metric includes using the breakpoint to trigger the comparing.

9. The method according to claim 1 , wherein:
the comparing a measured value for the performance metric to the target value for the performance metric includes keeping a count of a number of times a difference between the measured value for the performance metric and the target value for the performance metric is more than a preset tolerance; and
the ending the simulation when a specified condition based on said comparing is met includes ending the simulation when said count exceeds a preset limit.

10. A system comprising:
a processor; and
a memory, storing program code, which when executed on the processor, performs an operation of circuit design verification, the operation comprising:
loading a list of target values for a performance metric onto a hardware-accelerated simulator;
setting breakpoints to pause the hardware-accelerated simulator at defined intervals;
simulating, by the hardware-accelerated simulator, execution of a circuit design including collecting a checkpoint of the execution of the circuit design at a start of each defined interval;
during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric;
deleting, in response to the difference between the measured value for the performance metric and the target value for the performance value is within a preset tolerance, the collected checkpoint; and
ending the simulation when a specified condition based on said comparing is met.

11. The system according to claim 10 , wherein:
the comparing a measured value for the performance metric to the target value for the performance metric includes
at an end of each of the intervals, comparing the measured value for the performance metric to the target value for the performance metric, and
when the difference between the measured value for the performance metric and the target value for the performance metric is within the preset tolerance, ending the each pause and continuing the simulating execution of the circuit design.

12. The system according to claim 11 , wherein the comparing a measured value for the performance metric to the target value for the performance metric further includes:
when the difference between the measured value for the performance metric and the target value for the performance metric is outside the preset tolerance,
incrementing a count,
comparing the incremented count to a preset limit, and
when the incremented count does not exceed the preset limit, ending the each pause and continuing the simulating execution of the circuit design.

13. The system according to claim 10 , wherein the ending the simulation when a specified condition based on said comparing is met includes ending the simulation when the incremented count exceeds the preset limit.

14. A computer readable storage medium having stored thereon instructions that when executed by a processor causes the processor to perform an operation for circuit design verification, comprising:
loading a list of target values for a performance metric onto a hardware-accelerated simulator;
setting breakpoints to pause the hardware-accelerated simulator at defined intervals;
simulating, by the hardware-accelerated simulator, execution of a circuit design including collecting a checkpoint of the execution of the circuit design at a start of each defined interval;
during the simulating, using said breakpoints to pause the simulating at the defined times, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric;
deleting, in response to the difference between the measured value for the performance metric and the target value for the performance value is within a preset tolerance, the collected checkpoint; and
ending the simulation when a specified condition based on said comparing is met.

15. The computer readable storage medium according to claim 14 , wherein:
the setting breakpoints to pause the hardware-accelerated simulator at defined intervals includes setting the breakpoints to pause the hardware-accelerated simulator at ends of the defined intervals; and
the comparing a measured value for the performance metric to the target value for the performance metric includes
at the end of each of the intervals, comparing the measured value for the performance metric to the target value for the performance met

Assignees

• IBM

Inventors

• Pindicura Tharunachalam
• Xia Yan
• Yokum Karen
• Britto Vivek
• Srivatsan Shricharan
• Dhandapani Aishwarya

Classifications

• G06F11/1407

  Checkpointing the instruction stream · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F11/3652

  in-circuit-emulation [ICE] arrangements · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title