Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations
US-11544425-B2 · Jan 3, 2023 · US
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Bhalerao Abhijeet patents
Bhalerao Abhijeet is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Bhalerao Abhijeet |
| Total patents | 21 |
| First publication | Feb 19, 2015 |
| Latest publication | Jan 3, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations
US-11295046-B2 · Apr 5, 2022 · US
Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations
US-2020327204-A1 · Oct 15, 2020 · US
Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations
US-2020327209-A1 · Oct 15, 2020 · US
System, method and apparatus for preventing data loss due to memory defects using latches
US-9983920-B2 · May 29, 2018 · US
Data folding in 3D nonvolatile memory
US-9858009-B2 · Jan 2, 2018 · US
Partial bad block detection and re-use using EPWR for block based architectures
US-9804922-B2 · Oct 31, 2017 · US
Partially-bad block operation in 3-D nonvolatile memory
US-9760303-B2 · Sep 12, 2017 · US
Non-volatile memory systems with multi-write direction memory units
US-9728262-B2 · Aug 8, 2017 · US
Non-Volatile Memory Systems with Multi-Write Direction Memory Units
US-2017125104-A1 · May 4, 2017 · US
Recent patents
Latest publications not already listed above.
Data Folding in 3D Nonvolatile Memory
US-2017115884-A1 · Apr 27, 2017 · US
Partially-Bad Block Operation in 3-D Nonvolatile Memory
US-2017090762-A1 · Mar 30, 2017 · US
Initialization techniques for multi-level memory cells using multi-pass programming
US-9460780-B2 · Oct 4, 2016 · US
Memory system performance configuration
US-9442842-B2 · Sep 13, 2016 · US
System, Method and Apparatus for Preventing Data Loss Due to Memory Defects Using Latches
US-2016253231-A1 · Sep 1, 2016 · US
Initialization techniques for multi-level memory cells using multi-pass programming
US-2016211014-A1 · Jul 21, 2016 · US
System, method and apparatus for preventing data loss due to memory defects using latches
US-9372629-B2 · Jun 21, 2016 · US
Partial bad block detection and re-use using epwr for block based architectures
US-2016019111-A1 · Jan 21, 2016 · US
Adaptive EPWR (enhanced post write read) scheduling
US-9235470-B2 · Jan 12, 2016 · US
System, method and apparatus for preventing data loss due to memory defects using latches
US-2015355852-A1 · Dec 10, 2015 · US
Memory System Performance Configuration
US-2015052289-A1 · Feb 19, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Sandisk Technologies Inc | 16 |
| Sandisk Technologies Llc | 7 |
| Cnh Ind America Llc | 4 |
| Bhalerao Abhijeet | 1 |
| Kochar Mrinal | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0246 | 9 |
| G11C11/5628 | 8 |
| G11C16/0483 | 8 |
| G11C16/10 | 6 |
| G11C29/76 | 6 |