Partial bad block detection and re-use using epwr for block based architectures

Patent metadata

Field	Value
Publication number	US-2016019111-A1
Application number	US-201414336883-A
Country	US
Kind code	A1
Filing date	Jul 21, 2014
Priority date	Jul 21, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

Systems and methods for partial bad block reuse may be provided. Data may be copied from a block of a first memory to a block of a second memory. A post write read error may be detected in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory. The block of the second memory may be determined to be a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.

First claim

What is claimed is:

1 . A storage system comprising:
a solid state memory comprising a first memory and a second memory; a copy module configured to copy data from a block of the first memory to a block of the second memory; a post write read module configured to detect any post write read error in the data copied to the block of the second memory; and an error recovery module configured to determine that the block of the second memory is a partial bad block usable for storage in response to detection of a post write read error in a first portion of the data copied to the block of the second memory and no post write read error in a second portion of the data copied to the block of the second memory.

2 . The storage system of claim 1 , wherein the error recovery module is further configured to copy the first portion of the data from the block of the first memory to a cache in response to a determination that the block of the second memory is a partial bad block usable for storage.

3 . The storage system of claim 2 , wherein a logical address of the first portion of the data is mapped to a corresponding physical location in the cache.

4 . The storage system of claim 2 , wherein a logical address of the second portion of the data is mapped to a corresponding physical location in the block of the second memory.

5 . The storage system of claim 2 , wherein the cache is a binary cache.

6 . The storage system of claim 1 , wherein the error recovery module is configured to determine that the block of the second memory is the partial bad block usable for storage based on a determination that a number of pages in the first portion of the data is less than a threshold value.

7 . A storage device comprising:
a solid state memory comprising a first memory and a second memory; a copy module configured to copy data from a block of the first memory to a block of the second memory; a post write read module configured to detect any post write read error in the data copied to the block of the second memory; and an error recovery module configured to determine that the block of the second memory is a partial bad block in response to detection of a post write read error in a first portion of the data and no post write read error in a second portion of the data, wherein the partial bad block remains available for data storage despite the detection of the post write read error.

8 . The storage device of claim 7 , wherein the first memory has a first memory type and the second memory has a second memory type, and the copy module comprises a folding module.

9 . The storage device of claim 8 , wherein the first memory type is a single level cell (SLC) flash memory and the second memory type is a multi-level cell (MLC) flash memory.

10 . The storage device of claim 7 , wherein the error recovery module is configured to determine that the block of the second memory is the partial bad block usable for storage when a post write read of the second portion of the data succeeds even though a write error occurs when the second portion of the data is copied to the block of the second memory.

11 . The storage device of claim 10 , wherein the write error is a program error.

12 . The storage device of claim 10 , wherein the write error is a result of a slow to program bit.

13 . The storage device of claim 7 , wherein the block of the first memory is a different size than the block of the second memory.

14 . The storage device of claim 7 , wherein the first memory is a different size than the second memory.

15 . The storage device of claim 7 , wherein the post write read error is an enhanced post write read error.

16 . A method for partial bad block reuse, the method comprising:
copying data from a block of a first memory to a block of a second memory; detecting a post write read error in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory; and determining that the block of the second memory is a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.

17 . The method of claim 16 further comprising adding factory marked bad blocks to a free block list, wherein the block of the second memory is selected from the free block list.

18 . The method of claim 16 further comprising copying the first portion of the data from the block of the first memory to a cache in response to determining that the block of the second memory is a partial bad block usable for storage.

19 . The method of claim 16 , wherein at least one of the first memory and the second memory is a three dimensional memory.

Assignees

• Sandisk Technologies Inc

Inventors

• Kochar Mrinal
• Bhalerao Abhijeet
• Mcauley Derek
• Sagdeo Piyush

Classifications

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/2094 Primary

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/765

  in solid state disks · CPC title