Partially-bad block operation in 3-D nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9760303-B2
Application number	US-201514869686-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 29, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

First claim

It is claimed:

1. A method of operating a 3-D block-erasable nonvolatile memory formed in a plurality of levels of memory cells disposed above a substrate, each block having n separately-selectable sets of NAND strings connected in parallel, the method comprising:
identifying a plurality of partially-bad blocks, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings;
identifying operable sets of NAND strings within the partially-bad blocks;
mapping operable separately-selectable sets of NAND strings from two or more blocks to form one or more virtual blocks, each virtual block consisting of n separately-selectable sets of NAND strings;
assigning virtual block addresses individually to the one or more virtual blocks; subsequently, maintaining the virtual block addresses in a list;
subsequently, accessing the virtual blocks by the virtual block addresses, wherein the memory further includes good blocks that contain only operable separately-selectable sets of NAND strings and the memory further includes bad blocks that contain more than a threshold number of inoperable separately-selectable sets of NAND strings; and
maintaining a logical-to-physical map for data stored in the memory, the logical-to-physical map including an entry for each good block, an entry for each partially-bad block, and no entry for any bad block.

2. The method of claim 1 wherein the list is an available block list that includes addresses of the good blocks, the good blocks and the virtual blocks being equally available for storage of data.

3. The method of claim 1 wherein data is stored in the virtual blocks using a first redundancy scheme and data is stored in the good blocks using a second redundancy scheme, the first redundancy scheme having greater error correction capacity than the second redundancy scheme.

4. The method of claim 1 wherein data is stored in the virtual blocks in single level cell (SLC) format only and data is stored in at least some of the good blocks in multi-level cell (MLC) format.

5. The method of claim 1 wherein an individual virtual block is marked obsolete as a unit and is subsequently erased in a plurality of erase operations directed to the partially-bad blocks containing the separately-selectable sets of NAND strings forming the individual virtual block.

6. The method of claim 1 wherein the list is a list of scratch-pad blocks that are used only for short-term storage of small portions of data that are later copied to other locations.

7. A method of operating a 3-D nonvolatile memory formed in a plurality of levels of memory cells disposed above a substrate that are erasable in physical blocks, each physical block having n separately-selectable sets of vertical NAND strings, the method comprising:
identifying a plurality of partially-bad blocks from among blocks failing to meet test criteria, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings;
identifying operable sets of NAND strings within the partially-bad blocks;
mapping operable separately-selectable sets of NAND strings from two or more blocks to form a virtual block, the virtual block consisting of n separately-selectable sets of NAND strings;
assigning a virtual block address to the virtual block;
subsequently, maintaining the virtual block address in a spare block list; and
subsequently, accessing the virtual block by the virtual block address only when blocks meeting test criteria are not available,
wherein the n separately-selectable sets of vertical NAND strings of a physical block are physically ordered from position 1 to n and the separately-selectable sets of vertical NAND strings forming the virtual block are selected without regard to physical position.

8. The method of claim 7 wherein the n separately-selectable sets of vertical NAND strings of a physical block are physically ordered from position 1 to n and the separately-selectable sets of vertical NAND strings forming the virtual block are selected to include one separately-selectable set of vertical NAND strings from each position 1 to n.

9. The method of claim 7 wherein data is stored in the virtual block in a lower density format than data stored in blocks that meet test criteria.

10. The method of claim 7 wherein data is stored in the virtual block with a higher degree of redundancy than data stored in blocks that meet test criteria.

11. A nonvolatile memory system comprising:
a three-dimensional nonvolatile memory array that is monolithically formed in a plurality of physical levels of memory cells disposed above a substrate, and including a plurality of separately-erasable physical blocks, each physical block having n separately-selectable sets of vertical NAND strings;
a first subset of the plurality of physical blocks that meet predetermined criteria;
a second subset of the plurality of physical blocks that fail to meet the predetermined criteria;
a third subset of the plurality of physical blocks that fail to meet the predetermined criteria, and are each found to contain at least one operable separately-selectable set of vertical NAND strings;
a plurality of virtual blocks, an individual virtual block formed from operable separately-selectable sets of vertical NAND strings from two or more blocks from the third subset of the plurality of physical blocks, each virtual block having a unique virtual block address; and
a mapping unit that maps virtual block addresses to the separately-selectable sets of vertical NAND strings that form the virtual block so that access operations directed to a virtual block address are remapped to the separately-selectable sets of vertical NAND strings that form the virtual block.

12. The memory system of claim 11 wherein the n separately-selectable sets of vertical NAND strings of a physical block are physically ordered from position 1 to n and the separately-selectable sets of vertical NAND strings forming the virtual block include one separately-selectable set of vertical NAND strings from each position 1 to n.

13. The memory system of claim 11 further comprising a block selection unit that selects an available block for storage of new data, the block selection unit configured to only select virtual blocks when no block from the first subset of the plurality of blocks is available.

14. The memory system of claim 11 further comprising a redundancy unit configured to encode data with redundancy prior to storage, the redundancy unit configured to apply a lower level of redundancy to data stored in the first subset of the plurality of physical blocks and configured to apply a higher level of redundancy to data stored in the third subset of the plurality of physical blocks, the higher level of redundancy having capacity to correct a higher number of errors than the lower level of redundancy.

15. The memory system of claim 14 wherein the three-dimensional nonvolatile memory array is located on a first die, and the mapping unit and the redundancy unit are located on a second die.

16. The memory system of claim 15 wherein the first die and the second die are mounted on a printed circuit board in a memory system that is: a universal serial bus (USB) memory, a memory card, or a solid state drive.

Assignees

• Sandisk Technologies Llc

Inventors

• Ea Dennis S
• Baran Ivan
• Lee Aaron
• Kochar Mrinal
• Palityka Mikhail
• Ng Yew Yin
• Bhalerao Abhijeet

Classifications

• G11C29/88 Primary

  with partially good memories · CPC title

• G11C29/82

  for EEPROMs · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G11C29/765

  in solid state disks · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title