System, Method and Apparatus for Preventing Data Loss Due to Memory Defects Using Latches

US2016253231A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016253231-A1
Application numberUS-201615150325-A
CountryUS
Kind codeA1
Filing dateMay 9, 2016
Priority dateJun 9, 2014
Publication dateSep 1, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retrieved from the first selected memory location and written into the first buffer. Data in the first buffer can be matched to the user data in the second buffer to confirm a successful storage of the first user data in the memory system. A previously stored user data can be retrieved from a third selected memory location and written into a third buffer when the previously stored user data was stored in the memory system before the first user data.

First claim

Opening claim text (preview).

What is claimed is: 1 . A memory system including: a memory operating system logic including: computer readable instructions on computer readable media for receiving a first quantity of user data to be stored in the memory system; computer readable instructions on computer readable media for writing the first quantity of user data to a first location of the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first location to a first selected memory location within the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first location into a second location of the memory system when the first quantity of user data was successfully written to the first selected memory location; and computer readable instructions on computer readable media for confirming a quantity of stored data in the first location matches the first quantity of user data in the second location. 2 . The system of claim 1 , wherein the computer readable instructions on computer readable media for confirming the quantity of stored data in the first location matches the first quantity of user data in the second location, includes computer readable instructions on computer readable media for retrieving the quantity of stored data in the first selected memory location and writing the retrieved quantity of stored data into the first location. 3 . The system of claim 1 , further comprising: computer readable instructions on computer readable media for writing the first quantity of user data from the first location into a second selected memory location in the memory system when the first quantity of user data was not successfully written to the first selected memory location; and computer readable instructions on computer readable media for writing a second quantity of user data to a third selected memory location in the memory system when the second quantity of user data is stored in a third location of the memory system. 4 . The system of claim 3 , further comprising a dedicated error handling memory block in the memory system and wherein the second selected memory location is included in the dedicated error handling memory block. 5 . The system of claim 1 , further comprising a dedicated error handling memory block in the memory system. 6 . The system of claim 1 , further comprising a memory controller, wherein at least a portion of the memory operating system logic is included in the memory controller. 7 . The system of claim 1 , further comprising a memory array including a plurality of memory blocks of memory storage locations and at least a portion of the memory operating system logic is included in the memory array. 8 . The system of claim 1 , further comprising a memory array including a plurality of memory blocks of memory storage locations and at least a portion of a memory controller is included in the memory array. 9 . The system of claim 1 , further comprising a memory array including a plurality of memory blocks of memory storage locations and wherein the memory array includes a dedicated error handling memory block. 10 . The system of claim 1 , wherein the memory system is included in a computer system, the computer system including a processor coupled to the memory system by a data bus. 11 . The system of claim 1 , wherein at least a portion of the computer readable instructions on computer readable media are included in at least one integrated circuit. 12 . A data storage system comprising: a plurality of computer systems coupled by a data network, each one of the plurality of computer systems including: a memory system coupled to a processor by a data bus; and a memory operating system logic including: computer readable instructions on computer readable media for receiving a first quantity of user data to be stored in the memory system; computer readable instructions on computer readable media for writing the first quantity of user data to a first location of the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first location to a first selected memory location within the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first location into a second location of the memory system when the first quantity of user data was successfully written to the first selected memory location; and computer readable instructions on computer readable media for confirming a quantity of stored data in the first location matches the first quantity of user data in the second location. 13 . The system of claim 12 , wherein the memory system includes a plurality of memory storage locations and the memory operating system logic is for operating the plurality of memory storage locations. 14 . The system of claim 12 , wherein the computer readable instructions on computer readable media for confirming the quantity of stored data in the first location matches the first quantity of user data in the second location, includes computer readable instructions on computer readable media for retrieving the quantity of stored data in the first selected memory location and writing the retrieved quantity of stored data into the first location. 15 . The system of claim 12 , further comprising: computer readable instructions on computer readable media for writing the first quantity of user data from the first location into a second selected memory location in the memory system when the first quantity of user data was not successfully written to the first selected memory location; and computer readable instructions on computer readable media for writing a second quantity of user data to a third selected memory location in the memory system when the second quantity of user data is stored in a third location of the memory system. 16 . A mass data storage system comprising: a plurality of memory storage locations; and a memory operating system logic for storing data in the plurality of memory storage locations, the memory operating system logic including: computer readable instructions on computer readable media for receiving a first quantity of user data to be stored in the memory system; computer readable instructions on computer readable media for writing the first quantity of user data to a first location of the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first location to a first selected memory location within the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first location into a second location of the memory system when the first quantity of user data was successfully written to the first selected memory location; and computer readable instructions on computer readable media for confirming a quantity of stored data in the first location matches the first quantity of user data in the second location. 17 . The system of claim 16 , wherein the mass data storage system is external from a computer system and coupled to the computer system via a network interface and a data network. 18 . The system of claim 16 , wherein the mass data storage system is external from a plurality of computer systems and coupled to each one of the plurality of computer systems via one or more data networks.

Assignees

Inventors

Classifications

  • Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

  • using address translation or modifications · CPC title

  • using error correcting codes [ECC] or parity check · CPC title

  • Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

Patent family

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Frequently asked questions

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What does patent US2016253231A1 cover?
A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retriev…
Who is the assignee on this patent?
Sandisk Technologies Inc
What technology area does this patent fall under?
Primary CPC classification G06F11/079. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).