System, method and apparatus for preventing data loss due to memory defects using latches

US2015355852A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2015355852-A1
Application numberUS-201414300155-A
CountryUS
Kind codeA1
Filing dateJun 9, 2014
Priority dateJun 9, 2014
Publication dateDec 10, 2015
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retrieved from the first selected memory location and written into the first buffer. Data in the first buffer can be matched to the user data in the second buffer to confirm a successful storage of the first user data in the memory system. A previously stored user data can be retrieved from a third selected memory location and written into a third buffer when the previously stored user data was stored in the memory system before the first user data.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for operating a memory system comprising: receiving a first quantity of user data to be stored in the memory system; writing the first quantity of user data to a first buffer of the memory system; writing the first quantity of user data from the first buffer to a first selected memory location within a memory array of the memory system; writing the first quantity of user data from the first buffer into a second buffer of the memory system when the first quantity of user data was successfully written to the first selected memory location; retrieving a quantity of stored data in the first selected memory location and writing the retrieved quantity of stored data into the first buffer; and confirming the quantity of stored data in the first buffer matches the first quantity of user data in the second buffer. 2 . The method of claim 1 , further comprising writing the first quantity of user data from the first buffer into a second selected memory location in the memory system when the first quantity of user data was not successfully written to the first selected memory location. 3 . The method of claim 2 , further comprising writing a second quantity of user data to a third selected memory location in the memory system when the second quantity of user data is stored in a third buffer of the memory system. 4 . The method of claim 3 , wherein the third selected memory location is adjacent to the second selected memory location. 5 . The method of claim 3 , wherein the third selected memory location precedes the second selected memory location in the memory system. 6 . The method of claim 2 , wherein the second selected memory location is included in a dedicated error handling memory block in the memory system. 7 . The method of claim 6 , wherein the dedicated error handling memory block is included in the memory array. 8 . The method of claim 1 , wherein receiving the first quantity of user data to be stored in the memory system includes retrieving a quantity of previously stored user data in a third selected memory location and writing the retrieved quantity of previously stored user data into the third buffer when the previously stored user data was stored in the memory system before the first quantity of user data. 9 . The method of claim 8 , wherein writing the retrieved quantity of previously stored user data into the third buffer includes: writing the retrieved quantity of previously stored user data into the first buffer, before writing the first quantity of user data to the first buffer; and writing the retrieved quantity of previously stored user data from the first buffer into the third buffer. 10 . The method of claim 1 , further comprising writing the first quantity of user data from the second buffer into the second selected memory location in the memory system when the quantity of stored data in the first buffer does not match the first quantity of user data in the second buffer. 11 . The method of claim 10 , further comprising writing a second quantity of user data to the third selected memory location in the memory system when the second quantity of user data is stored in a third buffer of the memory system. 12 . The method of claim 1 , further comprising reporting a detected memory failure. 13 . The method of claim 12 , wherein reporting the detected memory failure includes identifying the memory location of the memory failure. 14 . A method for operating a memory system comprising: writing a second quantity of user data is into a third buffer of the memory system; receiving a first quantity of user data to be stored in the memory system, the second quantity of user data preceding the first quantity of user data; writing the first quantity of user data to a first buffer of the memory system; writing the first quantity of user data from the first buffer to a first selected memory location within a memory array of the memory system; writing the first quantity of user data from the first buffer into a second buffer of the memory system when the first quantity of user data was successfully written to the first selected memory location; retrieving a quantity of stored data in the first selected memory location and writing the retrieved quantity of stored data into the first buffer; confirming the quantity of stored data in the first buffer matches the first quantity of user data in the second buffer; and wherein when the first quantity of user data was not successfully written to the first selected memory location: writing the first quantity of user data from the first buffer into a second selected memory location in the memory system; and writing the second quantity of user data to a third selected memory location in the memory system, wherein the second selected memory location and the third memory location are included in a separate memory block from the first selected memory location. 15 . A memory system comprising: a memory array including a plurality of memory blocks of memory storage locations; a memory controller coupled to the memory array; and a memory operating system logic including: computer readable instructions on computer readable media for receiving a first quantity of user data to be stored in the memory system; computer readable instructions on computer readable media for writing the first quantity of user data to a first buffer of the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first buffer to a first selected memory location within the memory array of the memory system; computer readable instructions on computer readable media for writing the first quantity of user data from the first buffer into a second buffer of the memory system when the first quantity of user data was successfully written to the first selected memory location; computer readable instructions on computer readable media for retrieving a quantity of stored data in the first selected memory location and writing the retrieved quantity of stored data into the first buffer; and computer readable instructions on computer readable media for confirming the quantity of stored data in the first buffer matches the first quantity of user data in the second buffer. 16 . The system of claim 15 , wherein the memory operating system logic is included in the memory controller. 17 . The system of claim 15 , wherein the memory operating system logic is included in the memory array. 18 . The system of claim 15 , wherein the memory operating system logic is included in the memory array. 19 . The system of claim 15 , further comprising: computer readable instructions on computer readable media for writing the first quantity of user data from the first buffer into a second selected memory location in the memory system when the first quantity of user data was not successfully written to the first selected memory location; computer readable instructions on computer readable media for writing a second quantity of user data to a third selected memory location in the memory system when the second quantity of user data is stored in a third buffer of the memory system, wherein the second selected memory location is included in a dedicated error handling memory block in the memory system. 20 . The system of claim 19 , wherein the dedicated error handling memory block is included in the memory array.

Assignees

Inventors

Classifications

  • Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

  • Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

  • G11C29/025Primary

    in signal lines · CPC title

  • Online test · CPC title

  • using error correcting codes [ECC] or parity check · CPC title

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Frequently asked questions

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What does patent US2015355852A1 cover?
A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retriev…
Who is the assignee on this patent?
Sandisk Technologies Inc
What technology area does this patent fall under?
Primary CPC classification G11C29/025. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).