Semiconductor backside contact spacer engineering

Patent metadata

Field	Value
Publication number	US-2025261424-A1
Application number	US-202418438642-A
Country	US
Kind code	A1
Filing date	Feb 12, 2024
Priority date	Feb 12, 2024
Publication date	Aug 14, 2025
Grant date	—

Abstract

A semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first inner spacer and a second inner spacer disposed on a silicon layer, a third inner spacer disposed on the first inner spacer, a fourth inner spacer disposed on the second inner spacer, a gate region disposed on the silicon layer, and a source/drain region disposed on a backside source/drain contact, where an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer or the second inner spacer, and where the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer or the fourth inner spacer.

First claim

1 . A semiconductor structure, comprising:
a first inner spacer and a second inner spacer disposed on a silicon layer; a third inner spacer disposed on the first inner spacer; a fourth inner spacer disposed on the second inner spacer; a gate region disposed on the silicon layer; and a source/drain region disposed on a backside source/drain contact, wherein an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer or the second inner spacer, and wherein the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer or the fourth inner spacer.

2 . The semiconductor structure of claim 1 , wherein the gate region is a T-shaped gate region formed by the first inner spacer, the second inner spacer, the third inner spacer, and the fourth inner spacer.

3 . The semiconductor structure of claim 2 , wherein the first inner spacer and the second inner spacer are disposed on a same level of the semiconductor structure, and wherein the first inner spacer and the second inner spacer form a bottom region of the T-shaped gate region.

4 . The semiconductor structure of claim 3 , wherein the third inner spacer and the fourth inner spacer are disposed on another same level of the semiconductor structure, and wherein the third inner spacer and the fourth inner spacer form a top region of the T-shaped gate region.

5 . The semiconductor structure of claim 4 , wherein the top region of the T-shaped gate region is wider than the bottom region of the T-shaped gate region.

6 . The semiconductor structure of claim 1 , wherein the backside source/drain contact is isolated from the T-shaped gate region via the second inner spacer and the fourth inner spacer.

7 . The semiconductor structure of claim 1 , further comprising:
a nanosheet disposed on the T-shaped gate region, the third inner spacer, and the fourth inner spacer.

8 . The semiconductor structure of claim 1 , further comprising:
another source/drain region disposed on a placeholder, wherein an upper surface of the placeholder is disposed above a bottom surface of the first inner spacer or the second inner spacer, and wherein the upper surface of the placeholder is disposed below an upper surface of the third inner spacer or the fourth inner spacer.

9 . The semiconductor structure of claim 8 , wherein the placeholder is separated from the T-shaped gate region via the first inner spacer and the third inner spacer.

10 . The semiconductor structure of claim 8 , wherein the placeholder and the backside source/drain contact are disposed in a backside interlayer dielectric (ILD) layer;
wherein the backside ILD layer is disposed on a backside interconnect; wherein a frontside source/drain contact is disposed on the another source/drain region; wherein a frontside ILD layer is disposed on the source/drain region, a self-aligned gate cap, and a plurality of gate spacers; wherein a back-end-of-line interconnect is disposed on the frontside source/drain contact; and wherein a carrier wafer is bonded to the back-end-of-line interconnect.

11 . A method comprising:
forming a set of trenches in a semiconductor structure; forming a first inner spacer and a second inner spacer in the set of trenches; forming a third inner spacer and a fourth inner spacer in the set of trenches, wherein the third inner spacer is disposed on the first inner spacer, and wherein the fourth inner spacer is disposed on the second inner spacer; and forming a backside source/drain contact in the set of trenches, wherein an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer or the second inner spacer, and wherein the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer or the fourth inner spacer.

12 . The method of claim 11 , wherein the semiconductor structure includes:
a silicon substrate; a first sacrificial layer disposed on the silicon substrate, wherein the first sacrificial layer includes SiGe25%; a silicon layer disposed on the first sacrificial layer; a silicon etch stop layer disposed on the silicon layer, wherein the silicon etch stop includes SiGe55%; a second sacrificial layer disposed on the silicon etch stop; a first nanosheet layer disposed on the second sacrificial layer; a third sacrificial layer disposed on the first nanosheet layer; a second nanosheet layer disposed on the third sacrificial layer; a fourth sacrificial layer disposed on the second nanosheet layer; and a third nanosheet layer disposed on the fourth sacrificial layer.

13 . The method of claim 12 , wherein the first inner spacer and the second inner spacer are formed in the silicon etch stop layer.

14 . The method of claim 12 , wherein the third inner spacer and the fourth inner spacer are formed in the second sacrificial layer.

15 . The method of claim 11 , further comprising:
depositing a high-k metal gate material between the first inner spacer and the second inner spacer; and depositing the high-k metal gate material between the third inner spacer and the fourth inner spacer.

16 . The method of claim 15 , wherein the high-k metal gate material forms a T-shaped gate region.

17 . The method of claim 16 , wherein the backside source/drain contact is isolated from the T-shaped gate region via the second inner spacer and the fourth inner spacer.

18 . The method of claim 16 , wherein the high-k metal gate material between the first inner spacer and the second inner spacer forms a bottom region of the T-shaped gate region.

19 . The method of claim 18 , wherein the high-k metal gate material between the third inner spacer and the fourth inner spacer forms a top region of the T-shaped gate region.

20 . The method of claim 19 , wherein the top region of the T-shaped gate region is wider than the bottom region of the T-shaped gate region.

Assignees

• IBM

Inventors

• Arnold John Christopher
• Xie Ruilong
• Choi Kisik
• Yamashita Tenko
• Kumar Mahender
• Ramachandran Ravikumar

Classifications

• H10D30/0198

  forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title