Extended backside contact in stack nanosheet

Patent metadata

Field	Value
Publication number	US-2025031430-A1
Application number	US-202318356291-A
Country	US
Kind code	A1
Filing date	Jul 21, 2023
Priority date	Jul 21, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

First claim

What is claimed is:

1 . A microelectronic structure comprising:
a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices, wherein each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor; a gate cut located between the first row of stacked nano devices and the second row stacked nano devices; and an interconnect located within gate cut, wherein the interconnect is connected to a source/drain of one of the lower stacked transistors, wherein the interconnect includes a non-uniform backside surface.

2 . The microelectronic structure of claim 1 , wherein the interconnect includes an extension that extends under the source/drain of the lower stack transistor.

3 . The microelectronic structure of claim 2 , wherein the extension of the interconnect has a first height, when measured from a frontside surface to a backside surface, wherein interconnect has a section that is located adjacent to the extension of the interconnect, wherein the adjacent section of the interconnect has second height, when measured from a frontside surface to a backside surface.

4 . The microelectronic structure of claim 3 , wherein the second height is larger than the first height, wherein the difference in the first height and the second height causes the non-uniform backside surface of the interconnect.

5 . The microelectronic structure of claim 2 , further comprising a plurality of metal lines located on a backside of the first row of stacked nano devices and the second row stacked nano devices.

6 . The microelectronic structure of claim 5 , the extension of the interconnect extends across multiple metal lines of the plurality of metal lines.

7 . The microelectronic structure of claim 6 , further comprising:
a backside interlayer dielectric layer located between the extension of the interconnect and the plurality of metal lines.

8 . The microelectronic structure of claim 7 , wherein the interconnect is connected to one of the metal lines of the plurality of metal lines.

9 . The microelectronic structure of claim 8 , wherein the backside interlayer dielectric layer is in contact with a backside surface of the extension of the interconnect and a side surface of the interconnect.

10 . A microelectronic structure comprising:
a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices, wherein each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor; a gate cut located between the first row of stacked nano devices and the second row stacked nano devices, wherein the gate cut includes a dielectric liner and a dielectric fill layer; and an interconnect located within gate cut, wherein the interconnect is connected to a source/drain of one of the lower stacked transistors, wherein the interconnect includes a non-uniform backside surface.

11 . The microelectronic structure of claim 10 , wherein the interconnect includes an extension that extends under the source/drain of the lower stack transistor.

12 . The microelectronic structure of claim 11 , further comprising a plurality of metal lines located on a backside the first row of stacked nano devices and the second row stacked nano devices.

13 . The microelectronic structure of claim 12 , the extension of the interconnect extends across multiple metal lines of the plurality of metal lines.

14 . The microelectronic structure of claim 13 , further comprising:
a backside interlayer dielectric layer located between the extension of the interconnect and the plurality of metal lines.

15 . The microelectronic structure of claim 14 , wherein the interconnect is connected to one of the metal lines of the plurality of metal lines.

16 . The microelectronic structure of claim 15 , wherein the backside interlayer dielectric layer is in contact with a backside surface of the extension of the interconnect and a side surface of the interconnect.

17 . The microelectronic structure of claim 11 , wherein the extension of the interconnect is in direct contact with a backside surface of the source/drain of the lower stack and the extension of the interconnect is in direct contact with a first sidewall of the dielectric liner.

18 . The microelectronic structure of claim 17 , wherein the interconnect is direct contact with a second sidewall of the dielectric liner, wherein the first sidewall of the dielectric liner is the opposite the second sidewall of the dielectric liner.

19 . A method comprising:
forming a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and forming a second row of stack nano devices that includes a plurality of a second stacked nano FET devices, wherein each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor; forming a gate cut located between the first row of stacked nano devices and the second row stacked nano devices; and forming an interconnect located within gate cut, wherein the interconnect is connected to a source/drain of one of the lower stacked transistors, wherein the interconnect includes a non-uniform backside surface.

20 . The method of claim 19 , wherein the gate cut includes a dielectric liner and a dielectric fill layer, wherein the extension of the interconnect is in direct contact with a backside surface of the source/drain of the lower stack and the extension of the interconnect is in direct contact with a first sidewall of the dielectric liner, wherein the interconnect is direct contact with a second sidewall of the dielectric liner, and wherein the first sidewall of the dielectric liner is the opposite the second sidewall of the dielectric liner.

Assignees

• IBM

Inventors

• Khan Shahrukh
• Senapati Biswanath
• Bajpai Utkarsh
• Xie Ruilong
• Lanzillo Nicholas Anthony
• Yamashita Tenko
• Arnold John Christopher
• Zhang Chen
• Hook Terence B
• Wang Junli

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/019

  of FETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D30/501

  FETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title