Semiconductor passive device integration for silicon-on-insulator substrate

Patent metadata

Field	Value
Publication number	US-12489035-B2
Application number	US-202318324778-A
Country	US
Kind code	B2
Filing date	May 26, 2023
Priority date	May 26, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor structure includes logic device and passive device regions. The logic device region includes field effect transistors (FETs) having a gate structure and a source/drain region disposed on opposing sides of the gate structure. At least one source/drain region extends within a buried dielectric layer for electrically connecting a FET to a backside power rail (BPR). The passive device region includes passive devices disposed on a first side of a first semiconductor layer. A second semiconductor layer is disposed above a second side of the first semiconductor layer opposing the first side. A backside interlevel dielectric (BILD) is above the second semiconductor layer and the buried dielectric layer. The BPR is embedded within the BILD in the logic device region. A top surface of the BILD in the passive device region is coplanar with a top surface of the BPR and the BILD in the logic device region.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a logic device region including a plurality of field effect transistors, each field effect transistor including a gate structure and a source/drain region disposed on opposing sides of the gate structure, wherein at least one source/drain region of a field effect transistor extends within a buried dielectric layer for electrically connecting the field effect transistor to a backside power rail; a passive device region including a plurality of passive devices disposed on a first side of a first semiconductor layer and a second semiconductor layer disposed above a second side of the first semiconductor layer opposing the first side of the first semiconductor layer; and a backside interlevel dielectric located above the second semiconductor layer in the passive device region and above the buried dielectric layer in the logic device region, wherein the backside power rail is embedded within the backside interlevel dielectric in the logic device region, a top surface of the backside interlevel dielectric in the passive device region being coplanar with a top surface of the backside power rail and the backside interlevel dielectric in the logic device region.

2 . The semiconductor structure of claim 1 , further comprising:
a backside metal contact in direct contact with the at least one source/drain region of the field effect transistor extending within the buried dielectric layer for electrically connecting the field effect transistor to the backside power rail.

3 . The semiconductor structure of claim 1 , wherein the first semiconductor layer includes an epitaxially grown silicon layer.

4 . The semiconductor structure of claim 1 , wherein the second semiconductor layer includes an epitaxially grown silicon-germanium layer.

5 . The semiconductor structure of claim 1 , further comprising:
a plurality of metal contacts electrically connecting source/drain regions of field effect transistors not connected to the backside power rail to a first side of a back-end-of-line interconnect level, the plurality of metal contacts connecting the plurality of passive devices to the first side of the back-end-of-line interconnect level.

6 . The semiconductor structure of claim 1 , further comprising:
a power delivery network electrically connected to the backside power rail in the logic device region, the power delivery network located above the backside interlevel dielectric in the passive device region.

7 . The semiconductor structure of claim 1 , wherein the passive device region comprises a plurality of electrical components not requiring backside power supply, including at least one of capacitors and resistors.

8 . The semiconductor structure of claim 5 , further comprising:
a carrier wafer in contact with a second side of the back-end-of-line interconnect level opposing the first side of the back-end-of-line interconnect level.

9 . The semiconductor structure of claim 2 , wherein an interface between the second semiconductor layer and the backside interlevel dielectric in the passive device region is coplanar with an interface between the backside metal contact and the backside power rail.

10 . The semiconductor structure of claim 1 , wherein a thickness of the first semiconductor layer in the passive device region is equal to a thickness of the buried dielectric layer plus a height of an active channel region in the logic device region.

11 . A method of forming a semiconductor structure, comprising:
forming a logic device region including a plurality of field effect transistors, each field effect transistor including a gate structure and a source/drain region disposed on opposing sides of the gate structure, wherein at least one source/drain region of a field effect transistor extends within a buried dielectric layer for electrically connecting the field effect transistor to a backside power rail; forming a passive device region including a plurality of passive devices disposed on a first side of a first semiconductor layer and a second semiconductor layer disposed above a second side of the first semiconductor layer opposing the first side of the first semiconductor layer; and forming a backside interlevel dielectric above the second semiconductor layer in the passive device region and above the buried dielectric layer in the logic device region, wherein the backside power rail is embedded within the backside interlevel dielectric in the logic device region, a top surface of the backside interlevel dielectric in the passive device region being coplanar with a top surface of the backside power rail and the backside interlevel dielectric in the logic device region.

12 . The method of claim 11 , further comprising:
forming a backside metal contact in direct contact with the at least one source/drain region of the field effect transistor extending within the buried dielectric layer for electrically connecting the field effect transistor to the backside power rail.

13 . The method of claim 11 , wherein the first semiconductor layer includes an epitaxially grown silicon layer.

14 . The method of claim 11 , wherein the second semiconductor layer includes an epitaxially grown silicon-germanium layer.

15 . The method of claim 11 , further comprising:
forming a plurality of metal contacts for electrically connecting source/drain regions of field effect transistors not connected to the backside power rail to a first side of a back-end-of-line interconnect level, the plurality of metal contacts connecting the plurality of passive devices to the first side of the back-end-of-line interconnect level.

16 . The method of claim 11 , further comprising:
forming a power delivery network electrically connected to the backside power rail in the logic device region, the power delivery network located above the backside interlevel dielectric in the passive device region.

17 . The method of claim 11 , wherein the passive device region comprises a plurality of electrical components not requiring backside power supply, including at least one of capacitors and resistors.

18 . The method of claim 15 , further comprising:
forming a carrier wafer in contact with a second side of the back-end-of-line interconnect level opposing the first side of the back-end-of-line interconnect level.

19 . The method of claim 12 , wherein an interface between the second semiconductor layer and the backside interlevel dielectric in the passive device region is coplanar with an interface between the backside metal contact and the backside power rail.

20 . The method of claim 11 , wherein a thickness of the first semiconductor layer in the passive device region is equal to a thickness of the buried dielectric layer plus a height of an active channel region in the logic device region.

Assignees

• IBM

Inventors

• Xie Ruilong
• Choi Kisik
• Yamashita Tenko
• Arnold John Christopher
• Clevenger Lawrence A

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title