Techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access by a system
US-2026064605-A1 · Mar 5, 2026 · US
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Agarwal Ishwar patents
Agarwal Ishwar is listed as an inventor on 104 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Agarwal Ishwar |
| Total patents | 104 |
| First publication | Sep 29, 2016 |
| Latest publication | Mar 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Computing device with independently coherent nodes
US-2026029918-A1 · Jan 29, 2026 · US
Offloading of adaptive all reduce operations
US-2026010500-A1 · Jan 8, 2026 · US
Circuits and methods for coherent writing to host systems
US-12475075-B2 · Nov 18, 2025 · US
Non-posted write transactions for a computer bus
US-2025315391-A1 · Oct 9, 2025 · US
Confidential compute architecture integrated with direct swap caching
US-2025306978-A1 · Oct 2, 2025 · US
System, method and apparatus for hybrid mode memory having fine-grained interleaving of disparate address ranges
US-2025307134-A1 · Oct 2, 2025 · US
Computing device with independently coherent nodes
US-12430031-B2 · Sep 30, 2025 · US
Detecting and mitigating memory attacks
US-2025266082-A1 · Aug 21, 2025 · US
Confidential compute architecture integrated with direct swap caching
US-12353902-B2 · Jul 8, 2025 · US
Recent patents
Latest publications not already listed above.
Non-posted write transactions for a computer bus
US-12332813-B2 · Jun 17, 2025 · US
Addressing for disaggregated memory pool
US-12314174-B2 · May 27, 2025 · US
Detecting and mitigating memory attacks
US-12300304-B2 · May 13, 2025 · US
Detecting and mitigating memory attacks
US-2025111048-A1 · Apr 3, 2025 · US
Memory tiering techniques in computing systems
US-2025110829-A1 · Apr 3, 2025 · US
Direct swap caching with zero line optimizations
US-2025103339-A1 · Mar 27, 2025 · US
Systems and methods for flush plus reload cache side-channel attack mitigation
US-12259973-B2 · Mar 25, 2025 · US
Paging in thin-provisioned disaggregated memory
US-12242376-B2 · Mar 4, 2025 · US
Direct swap caching with zero line optimizations
US-12204909-B2 · Jan 21, 2025 · US
Memory tiering techniques in computing systems
US-12204408-B2 · Jan 21, 2025 · US
Managing and ranking memory resources
US-2025021248-A1 · Jan 16, 2025 · US
Detecting and mitigating memory attacks
US-12189764-B2 · Jan 7, 2025 · US
Systems and methods with integrated memory pooling and direct swap caching
US-12182620-B2 · Dec 31, 2024 · US
Computing device with independently coherent nodes
US-2024377953-A1 · Nov 14, 2024 · US
Managing and ranking memory resources
US-2024361947-A1 · Oct 31, 2024 · US
Managing and ranking memory resources
US-12039188-B2 · Jul 16, 2024 · US
Computing device with independently coherent nodes
US-11989416-B2 · May 21, 2024 · US
Detecting and mitigating memory attacks
US-2024112723-A1 · Apr 4, 2024 · US
Direct swap caching with zero line optimizations
US-2024103876-A1 · Mar 28, 2024 · US
Direct swap caching with noisy neighbor mitigation and dynamic address range assignment
US-11860783-B2 · Jan 2, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 52 |
| Microsoft Technology Licensing Llc | 52 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/5016 | 29 |
| G06F12/0284 | 26 |
| G06F13/1668 | 25 |
| G06F13/4282 | 23 |
| G06F3/067 | 23 |