Direct swap caching with zero line optimizations

Patent metadata

Field	Value
Publication number	US-12204909-B2
Application number	US-202318503869-A
Country	US
Kind code	B2
Filing date	Nov 7, 2023
Priority date	Apr 12, 2022
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

First claim

What is claimed:

1. A method for managing a system having a system level cache, a near memory, and a far memory, wherein cache lines associated with the system level cache can be swapped between the near memory and the far memory, the method comprising:
receiving a write request from a requestor to write non-zero data corresponding to an address; and
prior to writing the non-zero data:
analyzing a first metadata portion to determine whether a current cache line stored at the address in the near memory is guaranteed to be in the system level cache, and
analyzing a second metadata portion to determine whether a data portion associated with another cache line swappable with the current cache line comprises all zeros.

2. The method of claim 1 , further comprising upon determining that the current cache line stored at the address in the near memory is guaranteed to be in the system level cache and that the data portion associated with the another cache line swappable with the current cache line comprises all zeros, writing the non-zero data corresponding to the address in the near memory.

3. The method of claim 2 , wherein the writing the non-zero data corresponding to the address in the near memory results in a completion of the write request and there is no further interaction with the far memory in response to the write request.

4. The method of claim 1 , wherein the current cache line and the another cache line are stored in a direct-swap manner such that at a given time only one of the current cache line and the another cache line can be stored in the near memory.

5. The method of claim 1 , wherein the system further comprises a system level cache controller (SLCC), and wherein the method further comprises the SLCC tracking information regarding whether a cache line is guaranteed to be located in the near memory.

6. The method of claim 5 , further comprising the SLCC tracking information regarding whether a cache line located in the far memory comprises all zeros.

7. The method of claim 1 , wherein the requestor comprises a central processing unit (CPU) associated with the system, wherein the near memory comprises a first swappable range of memory addresses allocable to a process for execution by the CPU, wherein the far memory comprises a second swappable range of memory addresses allocable to the process for execution by the CPU, and wherein a ratio of a size of the first swappable range of memory addresses associated with the near memory and a size of the second swappable range of memory addresses associated with the far memory is fixed.

8. A system comprising a system level cache, a near memory, and a far memory, wherein cache lines associated with the system level cache can be swapped between the near memory and the far memory, the system comprising:
a near memory controller configured to receive a write request from a requestor to write non-zero data corresponding to an address; and
wherein the near memory controller is further configured to, prior to writing the non-zero data:
analyze a first metadata portion to determine whether a current cache line stored at the address in the near memory is guaranteed to be in the system level cache, and
analyze a second metadata portion to determine whether a data portion associated with another cache line swappable with the current cache line comprises all zeros.

9. The system of claim 8 , wherein the near memory controller is further configured to, upon determining that the current cache line stored at the address in the near memory is guaranteed to be in the system level cache and that the data portion associated with the another cache line swappable with the current cache line comprises all zeros, write the non-zero data corresponding to the address in the near memory.

10. The system of claim 8 , wherein the current cache line and the another cache line are stored in a direct-swap manner such that at a given time only one of the current cache line and the another cache line can be stored in the near memory.

11. The system of claim 8 , further comprising a system level cache controller (SLCC), wherein the SLCC is configured to track information regarding whether a cache line is guaranteed to be located in the near memory.

12. The system of claim 11 , wherein the SLCC is further configured to track information regarding whether a cache line located in the far memory comprises all zeros.

13. The system of claim 8 , wherein the requestor comprises a central processing unit (CPU) associated with the system, wherein the near memory comprises a first swappable range of memory addresses allocable to a process for execution by the CPU, wherein the far memory comprises a second swappable range of memory addresses allocable to the process for execution by the CPU, and wherein a ratio of a size of the first swappable range of memory addresses associated with the near memory and a size of the second swappable range of memory addresses associated with the far memory is fixed.

14. The system of claim 8 , wherein the near memory controller is further configured to provide grounded bits associated with a data portion as synthesized data portion.

15. A method for managing a system having a system level cache, a near memory, and a far memory, wherein cache lines associated with the system level cache can be swapped between the near memory and the far memory, the method comprising:
receiving a write request from a requestor to write non-zero data corresponding to an address;
upon determining that a current cache line stored at the address in the near memory is not guaranteed to be in the system level cache, prior to writing the non-zero data, initiating a read request to read another cache line stored at the address in the near memory; and
upon determining that a data portion associated with the another cache line comprises all zeros, writing the non-zero data corresponding to the address in the near memory, and modifying a metadata portion associated with the another cache line stored at the address in the near memory to indicate that the data portion associated with the another cache line does not contain all zeros.

16. The method of claim 15 , wherein the writing the non-zero data corresponding to the address in the near memory results in a completion of the write request and there is no further interaction with the far memory in response to the write request.

17. The method of claim 15 , wherein the current cache line and the another cache line are stored in a direct-swap manner such that at a given time only one of the current cache line and the another cache line can be stored in the near memory.

18. The method of claim 15 , wherein the system further comprises a system level cache controller (SLCC), and wherein the method further comprises the SLCC tracking information regarding whether a cache line is guaranteed to be located in the near memory.

19. The method of claim 18 , further comprising the SLCC tracking information regarding whether a cache line located in the far memory comprises all zeros.

20. The method of claim 15 , wherein the requestor comprises a central processing unit (CPU) associated with the system, wherein the near memory comprises a first swappable range of memory addresses allocable to a process for execution by the CPU, wherein the far memory comprises a second swappable range of memory addresses allocable to the process for execution by the CPU, and wherein a ratio of a size of the first swappable range of memory addresses associated with the near memory and a

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Agarwal Ishwar
• Chrysos George
• Rosell Martinez Oscar
• Bak Yevgeniy

Classifications

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F9/505

  considering the load · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F12/0886

  Variable-length word access · CPC title