Memory tiering techniques in computing systems

US12204408B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12204408-B2
Application numberUS-202318154164-A
CountryUS
Kind codeB2
Filing dateJan 13, 2023
Priority dateJul 9, 2021
Publication dateJan 21, 2025
Grant dateJan 21, 2025

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

First claim

Opening claim text (preview).

We claim: 1. A computer-implemented method of memory management, the method comprising: receiving a request from a processor to read data corresponding to a system memory section from a cache of the processor; retrieving, from a first section in a first memory, data and metadata, the metadata encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in a second memory; analyzing the data location information in the retrieved metadata to determine that the first section in the first memory currently contains data corresponding to the system memory section in the received request; and in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the first section in the first memory to the processor in response to the received request. 2. The computer-implemented method of claim 1 , further comprising: receiving a second request to read data corresponding to the system memory section from a cache of the processor; retrieving, from the first section in the first memory, second data and second metadata, the second metadata encoding data location information of multiple system memory sections in the first section of the first memory, the second section of the first memory, and one or more additional sections in the second memory; and analyzing the data location information in the retrieved second metadata to determine that the first section in the first memory does not currently contain data corresponding to the system memory section in the received second request. 3. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request: further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains data corresponding to the system memory section in the received second request; and retrieving the data from the second section in the first memory or the memory location in the second memory and providing the retrieved data to the processor in response to the received second request. 4. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request: further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request; upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request; and writing, to the first section in the first memory, the retrieved data from the second section in the first memory. 5. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request: further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request; upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request; writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and modifying the second metadata in the first memory to indicate that the data corresponding to the system memory section in the received second request is now in the first section of the first memory. 6. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request: further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received second request; upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request; writing, to the first section in the first memory, the retrieved data from the second section in the first memory; and writing, to the second section in the first memory, the retrieved data from the first section of the first memory. 7. The computer-implemented method of claim 2 , further comprising, in response to determining that the first section in the first memory currently does not contain data corresponding to the system memory section in the received second request: further analyzing the data location information in the retrieved second metadata to identify whether the second section in the first memory or a memory location in the second memory contains the data corresponding to the system memory section in the received request; upon determining that the second section in the first memory contains the data corresponding to the system memory section in the received second request, retrieving the data from the second section in the first memory and providing the retrieved data to the processor in response to the received second request; writing, to the first section in the first memory, the retrieved data from the second section in the first memory; writing, to the second section in the first memory, the retrieved data from the first section of the first memory; and modifying the second metadata in the first section of the first memory to indicate that: the data corresponding to the system memory section in the received second request is now in the first section of the first memory; and the data previously held in the first section of the first memory is now in the second section of the first memory. 8. The computer-implemented method of claim 1 , wherein: the metadata includes one or more bits; and the data location information includes combinations of the one or more bits that individually correspond to one of the multiple system memory sections; and analyzing the data location information includes: identifying a combination of the one or more bits; and determining whether the identified combination corresponds to the system memory section in the received request. 9. The computer-implemented method of claim 1 , wherein: the metadata includes one or more Error Checking and Correction (ECC) bits; and the data location information includes combinations of the one or more ECC bits that i

Assignees

Inventors

Classifications

  • with multilevel cache hierarchies · CPC title

  • using file system or storage system metadata · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

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Frequently asked questions

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What does patent US12204408B2 cover?
Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the sy…
Who is the assignee on this patent?
Microsoft Technology Licensing Llc
What technology area does this patent fall under?
Primary CPC classification G06F12/0811. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 21 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).