Circuits and methods for coherent writing to host systems

Patent metadata

Field	Value
Publication number	US-12475075-B2
Application number	US-202217692031-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Mar 10, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

First claim

What is claimed is:

1 . A circuit system comprising:
first logic circuitry that generates write data and a write command for a write request; second logic circuitry that receives the write data and the write command from the first logic circuitry, wherein the second logic circuitry stores the write data and the write command; and a host system that generates a write response in response to receiving the write command from the second logic circuitry, wherein the host system sends the write response to the second logic circuitry, and wherein the second logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the first logic circuitry.

2 . The circuit system of claim 1 , wherein the second logic circuitry comprises a first buffer circuit that stores the write data, a second buffer circuit that stores the write command, and a third buffer circuit that stores the write response received from the host system, and wherein the write data is provided from the first buffer circuit to the host system in response to a signal indicative of the write response being provided from the third buffer circuit to the first buffer circuit before the write response is provided to the first logic circuitry.

3 . The circuit system of claim 2 , wherein the first logic circuitry comprises a fourth buffer circuit that stores the write data and a fifth buffer circuit that stores the write command, and wherein the host system comprises a sixth buffer circuit that stores the write data and a seventh buffer circuit that stores the write command.

4 . The circuit system of claim 2 , wherein the first buffer circuit stores the write data and additional write data for an additional write request, and wherein the second logic circuitry comprises a fourth buffer circuit that stores an additional write command for the additional write request.

5 . The circuit system of claim 2 , wherein the first buffer circuit transfers the write data from a first clock domain to a second clock domain, wherein the second buffer circuit transfers the write command from the first clock domain to the second clock domain, and wherein the third buffer circuit transfers the write response from the second clock domain to the first clock domain.

6 . The circuit system of claim 1 , wherein the host system performs a write operation using the write command and the write data received from the second logic circuitry, wherein the write response is provided to the first logic circuitry from the second logic circuitry, and wherein the first logic circuitry is driven by a clock signal that has a frequency that is less than a frequency of a clock signal that drives the second logic circuitry.

7 . The circuit system of claim 1 , wherein the second logic circuitry comprises first, second, and third buffer circuits and arbitration and multiplexing circuitry that provides the write data generated from a first agent and a first identifier of the first agent to the first buffer circuit, wherein the arbitration and multiplexing circuitry provides the write command and the first identifier to the second buffer circuit,
wherein the arbitration and multiplexing circuitry provides additional write data generated by a second agent for an additional write request and a second identifier of the second agent to the first buffer circuit, and wherein the arbitration and multiplexing circuitry provides an additional write command for the additional write request and the second identifier to the third buffer circuit.

8 . A circuit system comprising:
first, second, and third buffer circuits; and arbitration and multiplexing circuitry that provides first write data generated from a first agent for a first write request and a first identifier of the first agent to the first buffer circuit, wherein the arbitration and multiplexing circuitry provides a first write command for the first write request and the first identifier to the second buffer circuit, wherein the arbitration and multiplexing circuitry provides second write data generated by a second agent for a second write request and a second identifier of the second agent to the first buffer circuit, and wherein the arbitration and multiplexing circuitry provides a second write command for the second write request and the second identifier to the third buffer circuit.

9 . The circuit system of claim 8 further comprising:
a fourth buffer circuit that stores the first write data, wherein the first write data is provided from the fourth buffer circuit to the arbitration and multiplexing circuitry;
a fifth buffer circuit that stores the first write command, wherein the first write command is provided from the fifth buffer circuit to the arbitration and multiplexing circuitry;
a sixth buffer circuit that stores the second write data, wherein the second write data is provided from the sixth buffer circuit to the arbitration and multiplexing circuitry; and
a seventh buffer circuit that stores the second write command, wherein the second write command is provided from the seventh buffer circuit to the arbitration and multiplexing circuitry.

10 . The circuit system of claim 8 further comprising:
fourth and fifth buffer circuits, wherein the first write data and the second write data are provided from the first buffer circuit to the fourth buffer circuit, wherein the first write command is provided from the second buffer circuit to the fifth buffer circuit, and wherein the second write command is provided from the third buffer circuit to the fifth buffer circuit.

11 . The circuit system of claim 8 further comprising:
a fourth buffer circuit, wherein the arbitration and multiplexing circuitry provides third write data generated by a third agent for a third write request and a third identifier of the third agent to the first buffer circuit, and wherein the arbitration and multiplexing circuitry provides a third write command for the third write request and the third identifier to the fourth buffer circuit.

12 . The circuit system of claim 8 , wherein the circuit system provides the first write data and the first write command to a host system concurrently based on the first write data and the first write command being associated with the first identifier, and wherein the circuit system provides the second write data and the second write command to the host system concurrently based on the second write data and the second write command being associated with the second identifier.

13 . The circuit system of claim 8 , wherein the first buffer circuit is a first first-in-first-out buffer circuit that stores the first and the second write data in an order received from the arbitration and multiplexing circuitry.

14 . The circuit system of claim 13 , wherein the second buffer circuit is a second first-in-first-out buffer circuit that stores the first write command and a third write command from the first agent in an order received from the arbitration and multiplexing circuitry, and wherein the third buffer circuit is a third first-in-first-out buffer circuit that stores the second write command and a fourth write command from the second agent in an order received from the arbitration and multiplexing circuitry.

15 . A method for providing a write request to a host system, the method comprising:
generating write data and a write command for the write request at first logic circuitry; storing the write data and the write command received from the first logic circuitry in second logic circuitry; generating a write response at the host s

Assignees

• Intel Corp

Inventors

• Nair Mohan
• Agarwal Ishwar
• Gupta Ashish
• Purohit Peeyush
• Govindaraj Vijay Pothi Raj
• Paliwal Nitish
• Boyapati Rahul
• Juan Minjer

Classifications

• G06F9/5016

  the resource being the memory · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F15/17331 Primary

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title

• G06F15/17 Primary

  using an input/output type connection, e.g. channel, I/O port · CPC title