Detecting and mitigating memory attacks

Patent metadata

Field	Value
Publication number	US-12189764-B2
Application number	US-202217828903-A
Country	US
Kind code	B2
Filing date	May 31, 2022
Priority date	May 31, 2022
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses within a memory hardware (e.g., a DRAM device) and determine whether a pattern of activations is indicative of a row hammer attack. This is determined using a counting mode for corresponding memory sub-banks. Where a likely row hammer attack is detected, the memory controller may activate a sampling mode (rather than the counting mode) for a particular sub-bank to identify which of the row addresses should be refreshed on the memory hardware. The implementations described herein provide a low computational cost alternative to heavy-handed detection mechanisms that require access to significant computing resources to accurately detect and mitigate row hammer attacks.

First claim

What is claimed is:

1. A method implemented by a memory controller for detecting and mitigating a row hammer attack on one or more memory rows of a dynamic random access memory (DRAM) device, comprising:
maintaining an access count table for a memory sub-bank, the access count table including memory row addresses within the memory sub-bank, a plurality of access counts indicating estimated activation counts for the memory row addresses, and a spillover count based on memory row accesses for at least one memory row address not included within the access count table;
detecting that the spillover count is greater than or equal to a threshold count, the threshold count being associated with a prediction of a possible aggressor row from the memory sub-bank;
based on detecting that the spillover count is greater than or equal to the threshold count, activating a sampling mode for the memory sub-bank by generating a random number and determining if the random number falls within a sampling threshold; and
reporting a memory row address as an aggressor address corresponding to the possible aggressor row based on whether the random number falls within the sampling threshold.

2. The method of claim 1 , further comprising maintaining a plurality of access count tables for a plurality of memory sub-banks including the memory sub-bank, the plurality of memory sub-banks corresponding to a memory bank of the DRAM device.

3. The method of claim 2 , wherein activating the sampling mode for the memory sub-bank comprises selectively activating the sampling mode while continuing to maintain additional access count tables from the plurality of access count tables for other sub-banks from the plurality of memory sub-banks.

4. The method of claim 1 , wherein maintaining the access count table includes:
detecting an activation of a first memory row address on the memory sub-bank;
determining that the first memory row address is not included within the access count table; and
incrementing the spillover count based on determining that the first memory row address is not included within the access count table.

5. The method of claim 4 , wherein incrementing the spillover count causes the spillover count to be greater than or equal to the threshold count.

6. The method of claim 1 , further comprising periodically clearing the access count table at a predetermined interval of time.

7. The method of claim 1 , wherein activating the sampling mode includes determining the sampling threshold based on a maximum activation count (MAC) determined for the DRAM device, wherein determining if the random number falls within the sampling threshold includes determining whether the random number is less than the sampling threshold.

8. The method of claim 7 , wherein a probability of the random number falling within the sampling threshold decreases as the MAC determined for the DRAM device increases.

9. The method of claim 1 , wherein reporting the memory row address as the aggressor address includes reporting a blast radius of two or more address rows to the DRAM device.

10. The method of claim 1 , wherein reporting the memory row address as the aggressor address includes issuing a refresh command that causes the DRAM device to refresh an address row of the aggressor address and one or more additional address rows adjacent to the address row.

11. The method of claim 1 , wherein the access count table is maintained in an SRAM structure on a memory controller coupled to the DRAM device.

12. The method of claim 1 , further comprising:
maintaining a record of reporting commands issued by the memory controller; and
reporting the memory row address based on the memory row address not being included within the record of reporting commands, when each value of the record of reporting commands is cleared at a predetermined interval of time, the predetermined interval of time being determined based on hardware specifications of the DRAM device.

13. A system, comprising:
a dynamic random access memory (DRAM) device including a plurality of memory banks, each memory bank from the plurality of memory banks including a plurality of memory sub-banks; and
a memory controller coupled to the DRAM device, the memory controller being configured to:
maintain an access count table for a memory sub-bank, the access count table including memory row addresses within the memory sub-bank, a plurality of access counts indicating estimated activation counts for the memory row addresses, and a spillover count based on row activations for at least one memory row address not included within the access count table;
detect that the spillover count is greater than or equal to a threshold count, the threshold count being associated with a prediction of a possible aggressor row from the memory sub-bank;
based on detecting that the spillover count is greater than or equal to the threshold count, activate a sampling mode for the memory sub-bank by generating a random number and determining if the random number falls within a sampling threshold; and
report a memory row address as an aggressor address corresponding to the possible aggressor row based on whether the random number falls within the sampling threshold.

14. The system of claim 13 , wherein the memory controller is further configured to maintain a plurality of access count tables for the plurality of memory sub-banks, and wherein activating the sampling mode for the memory sub-bank comprises selectively activating the sampling mode while continuing to maintain additional access count tables from the plurality of access count tables for other sub-banks from the plurality of memory sub-banks.

15. The system of claim 13 , wherein maintaining the access count table includes:
detecting an activation of a first memory row address on the memory sub-bank;
determining that the first memory row address is not included within the access count table; and
incrementing the spillover count based on determining that the first memory row address is not included within the access count table, wherein incrementing the spillover count causes the spillover count to be greater than or equal to the threshold count.

16. The system of claim 13 , wherein activating the sampling mode includes determining the sampling threshold based on a maximum activation count (MAC) determined for the DRAM device, wherein determining if the random number falls within the sampling threshold includes determining whether the random number is less than the sampling threshold.

17. The system of claim 13 , wherein reporting the memory row address as the aggressor address includes:
reporting a blast radius of two or more address rows to the DRAM device; or
issuing a refresh command that causes the DRAM device to refresh an address row of the aggressor address and one or more additional address rows adjacent to the address row.

18. A memory controller, the memory controller being configured to:
maintain an access count table for a memory sub-bank, the access count table including memory row addresses within the memory sub-bank, a plurality of access counts indicating estimated activation counts for the memory row addresses, and a spillover count based on row activations for at least one memory row address not included within the access count table;
detect that the spillover count is greater than or equal to a threshold count, the threshold count being associated with a prediction of a possible aggressor row from the memory sub-bank;
based on detecting that the spillover count is greater than or equal to the

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Agarwal Ishwar
• Saroiu Stefan
• Wolman Alastair
• Berger Daniel Sebastian

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C8/20

  Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G11C11/4078

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title