Computing device with independently coherent nodes

Patent metadata

Field	Value
Publication number	US-11989416-B2
Application number	US-202218049224-A
Country	US
Kind code	B2
Filing date	Oct 24, 2022
Priority date	Sep 9, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

A computing device includes a system-on-a-chip. The computing device comprises a network interface controller (NIC) that hosts a plurality of virtual functions and physical functions. Two or more compute nodes are coupled to the NIC. Each compute node is configured to operate a plurality of Virtual Machines (VMs). Each VM is configured to operate in conjunction with a virtual function via a virtual function driver. A dedicated VM operates in conjunction with a virtual NIC using a physical function hosted by the NIC via a physical function driver hosted by the compute node. The computing device further comprises a fabric manager configured to own a physical function of the NIC, to bind virtual functions hosted by the NIC to individual compute nodes, and to pool I/O devices across the two or more compute nodes.

First claim

The invention claimed is:

1. A computing device including a system-on-a-chip, comprising:
a network interface controller (NIC) that hosts a plurality of virtual functions and physical functions;
two or more compute nodes coupled to the NIC, each compute node configured to operate:
a plurality of Virtual Machines (VMs), each VM configured to operate in conjunction with a virtual function via a virtual function driver; and
a dedicated VM that operates in conjunction with a virtual NIC using a physical function hosted by the NIC via a physical function driver hosted by the compute node; and
a fabric manager configured to:
own a physical function of the NIC;
bind virtual functions hosted by the NIC to individual compute nodes; and
pool I/O devices across the two or more compute nodes.

2. The computing device of claim 1 , wherein the fabric manager and NIC are included in a central IO die communicatively coupled to each of the two or more compute nodes such that each compute node can access each IO device via the NIC.

3. The computing device of claim 1 , wherein each node comprises a virtual machine manager configured to host the physical function driver for the node.

4. The computing device of claim 1 , further comprising an IO memory management unit configured to facilitate pairing between each node and the NIC.

5. The computing device of claim 1 , wherein the fabric manager is further configured to virtualization resources across the two or more compute nodes.

6. The computing device of claim 1 , wherein the fabric manager is further configured to trap all downstream configuration and/or IO requests until a response can be emulated.

7. The computing device of claim 1 , wherein the fabric manager is configure to pool IO devices across the two or more compute nodes at least by leveraging single root I/O virtualization principles via the physical function.

8. The computing device of claim 1 , wherein the IO devices include memory units.

9. The computing device of claim 1 , wherein the fabric manager is further configured to program a host IO bridge for appending compute node identifications for upstream untranslated requests and/or for address translation services responses.

10. A computing device, comprising:
two or more compute nodes, each compute node comprising an independently coherent domain that is not coherent with other compute nodes; and
a central IO die communicatively coupled to each of the two or more compute nodes, the central IO die comprising:
a compute die port coupled to each compute node;
a memory port communicatively coupled to disaggregated memory at an external device via an IO port;
a memory controller communicatively coupled to natively attached memory; and
a plurality of distributed home agents communicatively coupled to each compute die port, communicatively coupled via a target address controller (TAD) to at least one memory port and at least one memory controller, each home agent configured to:
receive a request for either disaggregated memory or natively attached memory from a requesting compute node via a respective compute die port;
pass the received request to the TAD;
at the TAD, responsive to the received request indicating disaggregated memory, map the received request to a target memory port; and
at the TAD, responsive to the received request indicating natively attached memory, map the received request to a target memory controller.

11. The computing device of claim 10 , wherein the compute die port decodes an address within the received request and maps the decoded address to a respective home agent.

12. The computing device of claim 10 , wherein the target memory port is coupled to an external device comprising the disaggregated memory.

13. The computing device of claim 10 , wherein the home agent further comprises a cache currency mechanism comprising a snoop filter, the cache currency mechanism coupled to the TAD via content addressable memory.

14. The computing device of claim 13 , wherein the home agent is further configured to:
receive a request for memory access;
using the snoop filter, determine whether an updated copy of the request for memory access exists in the content addressable memory; and
present the updated copy of the request for retrieval.

15. The computing device of claim 13 , wherein the IO port further includes a serial bus interconnect (SBI) currency port configured to allow parallel lookups to external cache and to disaggregated memory.

16. The computing device of claim 15 , wherein the home agent is coupled to one or more additional external devices via the IO port.

17. The computing device of claim 16 , wherein the central IO die is configured to:
receive a request for an IO virtual address from the external device via an SBI root port;
at the SBI root port, translate the IO virtual address into a known physical address;
decode the known physical address such that any request for a given physical address targets the same home agent;
send the decoded known physical address to the respective home agent; and
at the home agent, translate the decoded known physical address for the external device.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Tavallaei Siamak
• Agarwal Ishwar

Classifications

• G06F12/0653

  with centralised address assignment · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F13/1668

  Details of memory controller · CPC title