Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US-2017352555-A1 · Dec 7, 2017 · US
Multilayered leadframes
Multilayered leadframes · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W70/451 |
| Official title | {Multilayered leadframes} |
| Display label | Multilayered leadframes |
| Total patents | 361 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 17 |
| 2016 | 17 |
| 2017 | 38 |
| 2018 | 32 |
| 2019 | 36 |
| 2020 | 47 |
| 2021 | 34 |
| 2022 | 35 |
| 2023 | 37 |
| 2024 | 29 |
| 2025 | 30 |
| 2026 | 9 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US-2017352610-A1 · Dec 7, 2017 · US
Semiconductor Package Including Flip Chip Mounted IC and Vertically Integrated Inductor
US-2017338171-A1 · Nov 23, 2017 · US
Insert-moulded lead frame and method for the production thereof
US-9808973-B2 · Nov 7, 2017 · US
Stack Frame for Electrical Connections and the Method to Fabricate Thereof
US-2017316954-A1 · Nov 2, 2017 · US
Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US-9805955-B1 · Oct 31, 2017 · US
Fan-out wafer level packaging structure
US-2017287738-A1 · Oct 5, 2017 · US
Printed wiring board and method for manufacturing the same
US-2017245365-A1 · Aug 24, 2017 · US
Stack frame for electrical connections and the method to fabricate thereof
US-9741590-B2 · Aug 22, 2017 · US
Wire connecting method and terminal
US-9716077-B2 · Jul 25, 2017 · US
Printed circuit board
US-2017202083-A1 · Jul 13, 2017 · US
Semiconductor package having a leadframe with multi-level assembly pads
US-2017179007-A1 · Jun 22, 2017 · US
Wiring circuit board and method of manufacturing the same
US-2017179005-A1 · Jun 22, 2017 · US
Packaged circuit with a lead frame and laminate substrate
US-2017162488-A1 · Jun 8, 2017 · US
Semiconductor packages and methods of packaging semiconductor devices
US-2017148722-A1 · May 25, 2017 · US
Stress reduction interposer for ceramic no-lead surface mount electronic device
US-2017150596-A1 · May 25, 2017 · US
Semiconductor device with stacked terminals
US-2017133316-A1 · May 11, 2017 · US
Stress reduction interposer for ceramic no-lead surface mount electronic device
US-9648729-B1 · May 9, 2017 · US
PCB based semiconductor package having integrated electrical functionality
US-9629246-B2 · Apr 18, 2017 · US
Packaged circuit with a lead frame and laminate substrate
US-9613889-B2 · Apr 4, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W70/451?
- CPC H10W70/451 is the Cooperative Patent Classification code for “Multilayered leadframes.”
- How many patents are filed under CPC H10W70/451 (Multilayered leadframes)?
- Our database includes 361 publications tagged with this CPC code.
- Is patent activity under CPC H10W70/451 growing?
- Publication counts under this code: 29 in 2024 vs 30 in 2025 (latest complete years).