Packaged circuit with a lead frame and laminate substrate

Patent metadata

Field	Value
Publication number	US-9613889-B2
Application number	US-201514663182-A
Country	US
Kind code	B2
Filing date	Mar 19, 2015
Priority date	May 23, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

First claim

What is claimed is:

1. A circuit comprising:
a lead frame having a first plurality of exposed terminals, a first surface of the lead frame defining a first plane and a second surface of the lead frame defining a second plane;
a laminate substrate between the first plane and the second plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface;
a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and
a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

2. The circuit of claim 1 , wherein the lead frame includes one or more side terminals extending from a first side thereof, wherein the laminate substrate is adjacent to the first side, the one or more side terminals coupled to a conductive portion of the laminate substrate.

3. The circuit of claim 2 , wherein the one or more side terminals are portions of conductive material that are thinner than a main portion of the lead frame.

4. The circuit of claim 3 , wherein the one or more side terminals extend onto a portion of the second surface of the laminate substrate and electrically couple to conductive pads on the second surface.

5. The circuit of claim 3 , wherein the one or more side terminals extend onto a portion of the first surface of the laminate substrate and electrically couple to conductive pads on the first surface.

6. The circuit of claim 1 , wherein the laminate substrate is composed of at least two layers of conductive material having at least one dielectric layer between the at least two layers, wherein a first layer of conductive material forms the first surface of the laminate substrate and a second layer of conductive material forms the second surface of the laminate substrate.

7. The circuit of claim 1 , wherein the first plurality of exposed terminals comprise leads that extend outward from a bottom side of the lead frame; and wherein the second plurality of exposed terminals comprise leads the extend outward from the first surface of the laminate substrate.

8. The circuit of claim 1 , wherein the first plurality of exposed terminals comprise pads on the first surface of the lead frame; and wherein the second plurality of exposed terminals comprise pads on the first surface of the laminate substrate.

9. The circuit of claim 1 , comprising:
a plurality of coupling members connected to an internal surface of the lead frame and to the second surface of the laminate substrate, wherein the plurality of coupling members include at least one of a wire bond or a copper clip.

10. The circuit of claim 1 , comprising:
molding compound on the lead frame and the laminate substrate and surrounding the first and second one or more dies.

11. The circuit of claim 1 , wherein the first one or more dies include one or more power transistors and the second one or more dies include one or more controllers.

12. An electronic device comprising:
one or more processing devices;
one or more memory devices communicatively coupled to the one or more processing devices; and
one or more power conversion systems coupled to the one or more processing devices and the one or more memory devices, the one or more power conversion systems including:
a lead frame having a first plurality of exposed terminals, a first surface of the lead frame defining a first plane, and a second surface of the lead frame defining a second plane;
a laminate substrate between the first plane and the second plane defined by the lead frame, adjacent to the lead frame and electrically coupled to the lead frame, the laminate substrate having an external surface including a second plurality of exposed terminals and an internal surface;
a first one or more power transistors mounted on the lead frame and electrically coupled to the lead frame; and
a controller die mounted on the internal surface of the laminate substrate and electrically coupled to the laminate substrate.

13. The electronic device of claim 12 , wherein the electronic device comprises one of desktop, laptop, or tablet computer, a set top box, or a battery charger.

14. The electronic device of claim 12 , wherein the lead frame includes one or more side terminals extending from a first side thereof, wherein the laminate substrate is adjacent to the first side, and the one or more side terminals overlap and are coupled to the internal surface of the laminate substrate.

15. The electronic device of claim 14 , wherein the one or more side terminals are portions of conductive material that are integral with the lead frame.

16. The electronic device of claim 12 , comprising:
one or more interconnect mechanisms coupled to the lead frame and the internal surface of the laminate substrate.

Assignees

• Intersil Americas LLC

Inventors

• Yin Jian
• Kelkar Nikhil Vishwanath
• Carpenter Jr Loyde Milton

Classifications

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title