PCB based semiconductor package having integrated electrical functionality

Patent metadata

Field	Value
Publication number	US-9629246-B2
Application number	US-201514811325-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Jul 28, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a metal baseplate having a die attach region and a peripheral region;
a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate; and
a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate, the multilayer circuit board comprising a plurality of interleaved signal and ground layers,
wherein a first one of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the transistor die,
wherein a first one of the ground layers is below the first signal layer,
wherein a second one of the signal layers is below the first ground layer and electrically connected to the first signal layer by insulated vias which extend through the first ground layer,
wherein a second one of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate.

2. The semiconductor package of claim 1 , wherein:
the first signal layer comprises a first plurality of signal metal tracks electrically connected to the RF terminal of the transistor die; and
the second signal layer comprises a first plurality of signal metal tracks electrically connected to respective ones of the first plurality of signal metal tracks of the first signal layer by the insulated vias.

3. The semiconductor package of claim 2 , wherein:
the first signal layer comprises a second plurality of signal metal tracks separate from the first plurality of signal metal tracks of the first signal layer; and
the first plurality of signal metal tracks of the second signal layer are electrically connected to respective ones of the first plurality of signal metal tracks of the first signal layer by a first group of the insulated vias and to respective ones of the second plurality of signal metal tracks of the first signal layer by a second group of the insulated vias.

4. The semiconductor package of claim 3 , wherein:
the first signal layer comprises a plurality of ground metal tracks separate from the first and the second plurality of signal metal tracks of the first signal layer; and
the second plurality of signal metal tracks and the plurality of ground metal tracks of the first signal layer are interleaved at the second side of the multilayer circuit board.

5. The semiconductor package of claim 4 , wherein the plurality of ground metal tracks of the first signal layer are electrically connected to the second ground layer at the first side of the multilayer circuit board by insulated vias which extend through the multilayer circuit board.

6. The semiconductor package of claim 3 , wherein the second plurality of signal metal tracks of the first signal layer are electrically connected to respective signal pads at the first side of the multilayer circuit board by insulated vias which extend through the multilayer circuit board.

7. The semiconductor package of claim 6 , further comprising ground pads at the first side of the multilayer circuit board which are separated from and interleaved with the signal pads.

8. The semiconductor package of claim 1 , wherein the first ground layer comprises a single metal sheet interposed between the first signal layer and the second signal layer.

9. The semiconductor package of claim 1 , wherein a harmonic termination resonator is formed in the second signal layer and configured to capture spurious harmonics present in a signal at the RF terminal of the transistor die.

10. The semiconductor package of claim 1 , wherein an impedance transformation network is formed in the second signal layer and configured to transform a lower impedance at the RF terminal of the transistor die to a higher impedance.

11. The semiconductor package of claim 10 , wherein the impedance transformation network comprises a radial stub formed in the second signal layer.

12. The semiconductor package of claim 1 , wherein:
the first signal layer comprises a power combiner and a plurality of metal tracks;
the metal tracks are electrically connected in parallel to the RF terminal of the transistor die at a first end of the metal tracks;
the metal tracks are connected to the power combiner at a second end of the metal tracks opposite the first end; and
the power combiner is configured to distribute current equally in amplitude and phase at each metal track.

13. The semiconductor package of claim 1 , wherein the second ground layer comprises ground pads and signal pads, wherein the ground pads are attached to the metal baseplate and extend beyond an exterior sidewall of the baseplate and are configured for attachment to another circuit board, and wherein the signal pads are spaced apart from the ground pads and positioned beyond the exterior sidewall of the baseplate and also configured for attachment to the same circuit board as the ground pads.

14. The semiconductor package of claim 13 , wherein the ground pads are electrically connected to each ground layer of the multilayer circuit board by insulated ground vias which extend at least partly through the multilayer circuit board, and wherein the signal pads are electrically connected to each signal layer of the multilayer circuit board by insulated signal vias which extend at least partly through the multilayer circuit board.

15. The semiconductor package of claim 1 , wherein the ground layers are electrically connected to one another by insulated ground vias which extend at least partly through the multilayer circuit board.

16. A semiconductor package, comprising:
a metal baseplate;
a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate;
a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate, the multilayer circuit board comprising a plurality of interleaved signal and ground layers, one of the signal layers being at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die, one of the ground layers being at the first side of the multilayer circuit board and attached to the metal baseplate;
power distribution structures formed in the signal layer at the second side of the multilayer circuit board; and
RF matching structures formed in a different one of the signal layers than the power distribution structures.

17. The semiconductor package of claim 16 , further comprising power combining structures formed in the signal layer at the second side of the multilayer circuit board and separate from the power distribution structures, wherein the power distribution structures are electrically connected to the power combining structures through the RF matching structures.

18. The semiconductor package of claim 17 , wherein the power combining structures are electrically connected to respective signal pads at the first side of the multilayer circuit board by insulated vias which extend through the multilayer circuit board.

19. The semiconductor package of claim 18 , further comprising ground pads at the first side of the multilayer circuit board which are electrically connected to the ground layers of the multilayer circuit board and interleaved with the signal pads.

20. A semiconductor assembly, comprising:
a substrate; and
a semiconductor package attached to the substrate and comprising:
a metal baseplate;
a semiconductor

Assignees

• Infineon Technologies Ag

Inventors

• Mu Qianli
• Gozzi Cristian
• Simcoe Michael
• Bigny Guillaume

Classifications

• H10W72/642

  being orthogonal to a side surface of the chip, e.g. in parallel arrangements · CPC title

• H10W72/647

  Dispositions of multiple strap connectors · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title