Device over patterned buried porous layer of semiconductor material
US-2024006524-A1 · Jan 4, 2024 · US
by making porous regions on the surface
by making porous regions on the surface · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P90/15 |
| Official title | {by making porous regions on the surface} |
| Display label | by making porous regions on the surface |
| Total patents | 71 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 4 |
| 2016 | 8 |
| 2017 | 7 |
| 2018 | 9 |
| 2019 | 5 |
| 2020 | 13 |
| 2021 | 2 |
| 2022 | 8 |
| 2023 | 6 |
| 2024 | 3 |
| 2025 | 4 |
| 2026 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Manufacturing and reuse of semiconductor substrates
US-2023127556-A1 · Apr 27, 2023 · US
Method of manufacturing semiconductor device
US-11562897-B1 · Jan 24, 2023 · US
Method of manufacturing semiconductor device
US-2023011018-A1 · Jan 12, 2023 · US
Method of electrochemically processing a substrate and integrated circuit device
US-11538689-B2 · Dec 27, 2022 · US
Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device
US-2022359194-A1 · Nov 10, 2022 · US
Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device
US-11476111-B2 · Oct 18, 2022 · US
Method of porosifying part of a semiconductor wafer
US-2022310380-A1 · Sep 29, 2022 · US
Method for partially removing a semiconductor wafer
US-11404262-B2 · Aug 2, 2022 · US
Semiconductor structure with one or more support structures
US-2022208691-A1 · Jun 30, 2022 · US
Semiconductor surface smoothing and semiconductor arrangement
US-11373857-B2 · Jun 28, 2022 · US
Foam in ion implantation system
US-11222768-B2 · Jan 11, 2022 · US
Direct growth methods for preparing diamond-assisted heat-dissipation silicon carbide substrates of GaN-HEMTs
US-11139176-B2 · Oct 5, 2021 · US
Sintered body and electrostatic chuck
US-10998216-B2 · May 4, 2021 · US
Method of electrochemically processing a substrate and integrated circuit device
US-2020411324-A1 · Dec 31, 2020 · US
Controlled residence CMP polishing method
US-10861702-B2 · Dec 8, 2020 · US
Biased pulse cmp groove pattern
US-2020381258-A1 · Dec 3, 2020 · US
Semiconductor surface smoothing and semiconductor arrangement
US-2020365385-A1 · Nov 19, 2020 · US
Porous semiconductor handle substrate
US-10784348-B2 · Sep 22, 2020 · US
Biased pulse CMP groove pattern
US-10777418-B2 · Sep 15, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P90/15?
- CPC H10P90/15 is the Cooperative Patent Classification code for “by making porous regions on the surface.”
- How many patents are filed under CPC H10P90/15 (by making porous regions on the surface)?
- Our database includes 71 publications tagged with this CPC code.
- Is patent activity under CPC H10P90/15 growing?
- Publication counts under this code: 3 in 2024 vs 4 in 2025 (latest complete years).