Porous semiconductor handle substrate

Patent metadata

Field	Value
Publication number	US-10784348-B2
Application number	US-201715669704-A
Country	US
Kind code	B2
Filing date	Aug 4, 2017
Priority date	Mar 23, 2017
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
an active device layer on a front-side surface of a semiconductor layer on an insulator layer of a semiconductor on insulator (SOI) device substrate;
a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer; and
a semiconductor handle substrate having a porous semiconductor layer contacting the second surface of the front-side dielectric layer and distal from the SOI device substrate, in which the semiconductor handle substrate is uniformly doped, and the porous semiconductor layer comprises a high porosity portion corresponding to dicing streets on the semiconductor device substrate, a first low porosity portion and a second low porosity portion adjacent to and side-by-side with the high porosity portion, the high porosity portion between the first low porosity portion and the second low porosity portion.

2. The IC of claim 1 , in which the porous semiconductor layer has a depth greater than 10 microns.

3. The IC of claim 1 , in which the semiconductor handle substrate comprises a bulk silicon wafer having the porous semiconductor layer.

4. The IC of claim 1 , in which the porous semiconductor layer is sealed or capped with oxide.

5. The IC of claim 1 , further comprising an oxide and/or adhesive between the porous semiconductor layer of the semiconductor handle substrate and the front-side dielectric layer.

6. The IC of claim 1 , further comprising an oxide within pores of the porous semiconductor layer of the semiconductor handle substrate.

7. The IC of claim 1 , in which the porous semiconductor layer comprises sealed oxide porous silicon.

8. The IC of claim 1 , in which the porous semiconductor layer comprises different porosities.

9. The IC of claim 1 , in which the porous semiconductor layer comprises different levels of porosity in different layers.

10. The IC of claim 9 , in which the different levels of porosity are graded or stepped.

11. The IC of claim 1 , in which the porous semiconductor layer comprises a 50 micron thick layer proximate to the front-side dielectric layer.

12. The IC of claim 1 , integrated into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

13. An integrated circuit (IC), comprising:
an active device layer on a front-side surface of a semiconductor layer on an insulator layer of a semiconductor on insulator (SOI) device substrate;
a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer; and
means for reducing radio frequency (RF) harmonics contacting the second surface of the front-side dielectric layer and distal from the SOI device substrate, and the means for reducing RF harmonics comprising a high porosity portion corresponding to dicing streets on the semiconductor device substrate, a first low porosity portion and a second low porosity portion adjacent to and side-by-side with the high porosity portion, the high porosity portion between the first low porosity portion and the second low porosity portion.

14. The IC of claim 13 , integrated into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

Assignees

• Qualcomm Inc

Inventors

• Fanelli Stephen Alan
• Hammond Richard

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title