Selective etching process for SiGe and doped epitaxial silicon
US-12062571-B2 · Aug 13, 2024 · US
Singulating wafers or substrates into multiple chips, i.e. dicing
Singulating wafers or substrates into multiple chips, i.e. dicing · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P58/00 |
| Official title | Singulating wafers or substrates into multiple chips, i.e. dicing |
| Display label | Singulating wafers or substrates into multiple chips, i.e. dicing |
| Total patents | 427 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 31 |
| 2016 | 43 |
| 2017 | 34 |
| 2018 | 36 |
| 2019 | 45 |
| 2020 | 38 |
| 2021 | 24 |
| 2022 | 34 |
| 2023 | 46 |
| 2024 | 45 |
| 2025 | 41 |
| 2026 | 10 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device having recessed edges and method of manufacture
US-2016379956-A1 · Dec 29, 2016 · US
Semiconductor die connection system and method
US-9520340-B2 · Dec 13, 2016 · US
Hybrid active-field gap extended drain mos transistor
US-2016343852-A1 · Nov 24, 2016 · US
Opening in a multilayer polymeric dielectric layer without delamination
US-9502365-B2 · Nov 22, 2016 · US
Method for forming crack-stopping structures
US-2016336274-A1 · Nov 17, 2016 · US
Semiconductor Device Structure and Method
US-2016336416-A1 · Nov 17, 2016 · US
Semiconductor device and manufacturing method thereof
US-9484318-B2 · Nov 1, 2016 · US
Optoelectronic device packages
US-2016306072-A1 · Oct 20, 2016 · US
Dummy metal structure and method of forming dummy metal structure
US-9472509-B2 · Oct 18, 2016 · US
Packages with stress-reducing structures and methods of forming same
US-9472481-B2 · Oct 18, 2016 · US
Process for Forming Package-on-Package Structures
US-2016293588-A1 · Oct 6, 2016 · US
Semiconductor workpiece having a semiconductor substrate with at least two chip areas
US-9461004-B2 · Oct 4, 2016 · US
Method of forming a semiconductor die
US-9437493-B2 · Sep 6, 2016 · US
Chip Scale Package
US-2016225733-A1 · Aug 4, 2016 · US
Dummy metal structure and method of forming dummy metal structure
US-9406608-B2 · Aug 2, 2016 · US
Dicing method for power transistors
US-2016204074-A1 · Jul 14, 2016 · US
Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
US-9368344-B2 · Jun 14, 2016 · US
Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US-9355997-B2 · May 31, 2016 · US
Wafer processing method
US-2016126138-A1 · May 5, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P58/00?
- CPC H10P58/00 is the Cooperative Patent Classification code for “Singulating wafers or substrates into multiple chips, i.e. dicing.”
- How many patents are filed under CPC H10P58/00 (Singulating wafers or substrates into multiple chips, i.e. dicing)?
- Our database includes 427 publications tagged with this CPC code.
- Is patent activity under CPC H10P58/00 growing?
- Publication counts under this code: 45 in 2024 vs 41 in 2025 (latest complete years).