Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9484318-B2
Application number	US-201414181912-A
Country	US
Kind code	B2
Filing date	Feb 17, 2014
Priority date	Feb 17, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first layer and a second layer over the first layer;
a bump disposed over the second layer;
a molding disposed over the second layer and surrounding the bump, wherein the second layer includes a protruded portion protruding from a sidewall of the molding adjacent to a periphery of the substrate; and
a retainer disposed on the second layer, wherein the retainer is disposed between the molding and the periphery of the substrate, and the retainer includes silicon nitride (SiN), silicon dioxide (SiO2), or silicon oxynitride (SiON);
wherein an included angle of the sidewall of the molding and an upper surface of the molding is smaller than ninety degrees;
wherein the retainer has a trapezoidal cross-section, a bottom base of the trapezoidal cross-section is in contact with the second layer, an upper base of the trapezoidal cross-section is coplanar with a portion of a too surface of the molding immediately adjacent to the retainer, and the bottom base of the trapezoidal cross-section is longer than the upper base of the trapezoidal cross-section.

2. The semiconductor device of claim 1 , wherein the first layer includes a protruded portion protruding from a sidewall of the molding adjacent to the periphery of the substrate.

3. The semiconductor device of claim 1 , wherein a sidewall of the second layer is aligned with a sidewall of the first layer adjacent to the periphery of the substrate.

4. The semiconductor device of claim 1 , wherein the molding has an inclined sidewall adjacent to the periphery of the substrate.

5. A semiconductor device, comprising:
a substrate including a first layer and a second layer over the first layer;
a bump disposed over the second layer;
a molding disposed over the second layer and surrounding the bump; and
a retainer disposed on the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate, and the retainer includes silicon nitride (SiN), silicon dioxide (SiO2), or silicon oxynitride (SiON);
wherein a top end of the retainer is lower than or equal to a top end of the bump;
wherein the retainer has a trapezoidal cross-section, a bottom base of the trapezoidal cross-section is in contact with the second layer, an upper base of the trapezoidal cross-section is coplanar with a portion of a top surface of the molding immediately adjacent to the retainer, and the bottom base of the trapezoidal cross-section is longer than the upper base of the trapezoidal cross-section.

6. The semiconductor device of claim 5 , wherein the retainer includes a blocking ring surrounding the molding.

7. The semiconductor device of claim 5 , wherein the retainer includes a plurality of blocking walls adjacent to the periphery of the substrate.

8. The semiconductor device of claim 5 , wherein the retainer has an inclined sidewall adjacent to the periphery of the substrate.

9. The semiconductor device of claim 5 , wherein an included angle of a sidewall of the retainer and an upper surface of the retainer is larger than ninety degrees.

10. The semiconductor device of claim 5 , wherein the second layer includes a protruded portion protruding from a sidewall of the retainer adjacent to the periphery of the substrate.

11. A method of manufacturing a semiconductor device, comprising:
providing a substrate including a first layer and a second layer over the first layer;
disposing a plurality of bumps on the second layer;
using silicon nitride (SiN), silicon dioxide (SiO2), or silicon oxynitride (SiON) to form a retainer on the second layer and surrounding the plurality of bumps; and
disposing a molding on the second layer, wherein the molding is disposed between the bumps and the retainer;
wherein the retainer has a trapezoidal cross-section, a bottom base of the trapezoidal cross-section is in contact with the second layer, an upper base of the trapezoidal cross-section is coplanar with a portion of a top surface of the molding immediately adjacent to the retainer, and the bottom base of the trapezoidal cross-section is longer than the upper base of the trapezoidal cross-section.

12. The method of claim 11 , further comprising:
removing the retainer from the second layer to form a recess between at least two of the bumps, wherein the recess exposes at least a portion of scribe lines of the substrate; and
cutting the substrate into a plurality of dies from the recess.

13. The method of claim 12 , wherein the cutting of the substrate is implemented by a laser saw.

14. The method of claim 11 , further comprising cutting the substrate into a plurality of dies from a recess adjacent to the retainer.

15. The method of claim 11 , wherein the forming of the retainer includes performing a photolithographic process to form a plurality of blocking walls on scribe lines of the substrate.

16. The method of claim 11 , wherein the forming of the retainer includes performing a photolithographic process to form a plurality of blocking rings, and the molding is disposed inside the blocking rings.

17. The method of claim 11 , wherein the disposing of the molding includes performing a screen stencil process.

18. The method of claim 11 , wherein a sidewall of the retainer is not aligned with a sidewall of the second layer, thereby forming a stepped configuration.

19. The method of claim 11 , wherein the top end of the retainer is lower than or equal to the top end of the bump.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shao Tung-Liang
• Lai Yu-Chia
• Tu Hsien-Ming
• Huang Chang-Pin
• Yang Ching-Jung

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title