Dummy metal structure and method of forming dummy metal structure

Patent metadata

Field	Value
Publication number	US-9406608-B2
Application number	US-201414515836-A
Country	US
Kind code	B2
Filing date	Oct 16, 2014
Priority date	Oct 16, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

First claim

What is claimed is:

1. A method comprising:
forming a first metal interconnection layer above a substrate of a semiconductor wafer and between a plurality of die regions, the first metal interconnection layer including a first plurality of dummy vertical interconnect accesses (VIAs) and a first plurality of dummy metal lines,
wherein the first plurality of dummy metal lines laterally connect the first plurality of dummy VIAs;
forming a second metal interconnection layer above the first metal interconnection layer and between the plurality of die regions, the second metal interconnection layer including a second plurality of dummy VIAs and a second plurality of dummy metal lines,
wherein the second plurality of dummy VIAs vertically connect the first plurality of dummy metal lines with the second plurality of dummy metal lines, and the second plurality of dummy metal lines laterally connect the second plurality of dummy VIAs; and
forming one or more of the first metal interconnection layer and the second metal interconnection layer, in alternating order, in forming remaining metal interconnection layers of the semiconductor wafer,
wherein each of the first plurality of dummy metal lines and the second plurality of dummy metal lines includes a first set of the dummy metal lines that extend in a first direction and a second set of the dummy metal lines that extend in a second direction.

2. The method according to claim 1 , comprising:
forming the first plurality of dummy metal lines across substantially all of an area between the plurality of die regions; and
forming the second plurality of dummy metal lines across substantially all of the area between the plurality of die regions.

3. The method according to claim 1 , wherein the second direction is orthogonal to the first direction.

4. The method according to claim 1 , wherein the first set and the second set within each of the first plurality of dummy metal lines and the second plurality of dummy metal lines connect at intersections to form junction areas.

5. The method according to claim 4 , wherein widths and lengths of the junction areas are larger than widths of the first plurality of dummy metal lines and the second plurality of dummy metal lines.

6. The method according to claim 1 , further comprising:
forming foundation metal interconnection pads within the substrate and/or on a top surface of the substrate; and
forming the first plurality of dummy VIAs connected to the foundation metal interconnection pads.

7. The method according to claim 1 , comprising:
forming the first metal interconnection layer and the second metal interconnection layer separated from the plurality of die regions by a gap.

8. The method according to claim 1 , wherein a pattern formed by the first plurality of dummy metal lines is different from a pattern formed by the second plurality of dummy metal lines.

9. A method comprising:
forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines,
wherein the plurality of dummy metal lines laterally connect the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connect a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, wherein the second metal interconnection layer is below the first metal interconnection layer;
forming foundation metal interconnection pads within the substrate; and
forming the plurality of dummy VIAs of a metal interconnection layer immediately above the substrate connected to the foundation metal interconnection pads,
wherein the plurality of dummy metal lines of each metal interconnection layer extend across substantially all of an area between the plurality of die regions, and the plurality of dummy metal lines of each metal interconnection layer include a first set of the dummy metal lines that extend in a first direction and a second set of the dummy metal lines that extend in a second direction.

Assignees

• Globalfoundries Inc

Inventors

• Cho Jae Kyu
• Gao Shan

Classifications

• H10W20/031 Primary

  of conductive parts of the interconnections · CPC title

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title