Opening in a multilayer polymeric dielectric layer without delamination

Patent metadata

Field	Value
Publication number	US-9502365-B2
Application number	US-201414576784-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 31, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.

First claim

What is claimed is:

1. A process of forming an integrated circuit, comprising the steps:
coating the integrated circuit with a first layer of a photosensitive polymer dielectric;
exposing a first opening in the first layer using a first opening photo mask;
developing the first layer to form the first opening with a first layer edge;
curing the first layer;
coating the integrated circuit with an overlying layer of a photosensitive polymer dielectric;
exposing an IC opening in the overlying layer of photosensitive polymer layer using an IC opening photomask;
developing the overlying layer of photosensitive polymer to form an IC opening;
curing the overlying layer;
coating the integrated circuit with a second layer of a photosensitive polymer dielectric;
exposing a second opening in the second layer of photosensitive polymer layer using a second opening photomask;
developing the second layer of photosensitive polymer to form the second opening;
wherein the IC opening and the first opening are concentric;
wherein the IC opening is smaller than the first opening; and
wherein the overlying layer covers the first layer edge.

2. The process of claim 1 , wherein:
the second layer overlies the first layer and the overlying layer overlies the second layer;
the second opening is larger than the first opening and wherein the second opening and the first opening are concentric;
the second layer is stair stepped away from the first layer edge; and
the overlying layer covers the second layer edge.

3. The process of claim 1 , wherein:
the second layer overlies the first layer and underlies the overlying layer;
the second opening is larger than the IC opening and the second opening is smaller than the first opening and wherein the second opening and the first opening are concentric;
the second layer covers the first layer edge; and
wherein the overlying layer covers the second layer edge.

4. The process of claim 1 , wherein the IC opening is an IC bondpad opening.

5. The process of claim 1 , wherein the IC opening is a scribe seal opening.

6. The process of claim 1 , wherein the photosensitive polymer dielectric a photosensitive polymer such as polyimide, polybenzobisoxazole (PBO), SU-8 (epoxy-based photosensitive polymer), or BCB (benzocyclobutene-based photosensitive polymer).

7. The integrated circuit of claim 1 , wherein the photosensitive polymer dielectric is a photosensitive polyimide.

8. The process of claim 1 , wherein:
the second layer overlies the first layer and the overlying layer;
the second opening is larger than the IC opening; and
the second opening and the first opening are concentric.

9. The process of claim 1 , further comprising:
coating the integrated circuit with a third layer of a photosensitive polymer dielectric wherein the third layer overlies the first layer, the second layer, and the overlying layer;
exposing a third opening in the third layer using a third opening photo mask, wherein the third opening is larger than the IC opening and the first opening and wherein the third opening and the first opening are concentric;
developing the third layer to form the third opening with a third layer edge;
curing the third layer;
wherein the third layer is stair-stepped from the IC opening.

10. A process of forming an integrated circuit, comprising the steps:
coating the integrated circuit with a first layer of a photosensitive polymer dielectric;
forming a first opening with a first layer edge in the first layer;
curing the first layer;
coating the integrated circuit with a second layer of a photosensitive polymer dielectric wherein the second layer overlies the first layer;
forming a second opening with a second layer edge in the second layer;
curing the second layer;
coating the integrated circuit with an overlying layer of a photosensitive polymer dielectric, wherein the overlying layer overlies both the first layer and the second layer;
forming an IC opening in the overlying layer; and
curing the overlying layer;
wherein the IC opening and the first opening are concentric;
wherein the IC opening is smaller than the first opening and the second opening;
wherein the second layer is stair stepped away from the first layer edge; and
wherein the overlying layer completely covers the first layer edge and the second layer edge.

11. The process of claim 10 , further comprising:
coating the integrated circuit with a third layer of a photosensitive polymer dielectric wherein the third layer overlies the first layer, the second layer, and the overlying layer;
exposing a third opening in the third layer using a third opening photo mask, wherein the third opening is larger than the IC opening and the first opening and wherein the third opening and the first opening are concentric;
developing the third layer to form the third opening with a third layer edge;
curing the third layer;
wherein the third layer is stair stepped away from the IC opening.

12. The process of claim 10 , wherein the photosensitive polymer dielectric a photosensitive polymer such as polyimide, polybenzobisoxazole (PBO), SU-8 (epoxy-based photosensitive polymer), or BCB (benzocyclobutene-based photosensitive polymer).

13. The integrated circuit of claim 10 , wherein the photosensitive polymer dielectric is a photosensitive polyimide.

14. A process of forming an integrated circuit, comprising the steps:
coating the integrated circuit with a first layer of a photosensitive polymer dielectric;
forming a first opening with a first layer edge in the first layer;
curing the first layer;
coating the integrated circuit with an overlying layer of a photosensitive polymer dielectric;
forming an IC opening in the overlying layer;
curing the overlying layer;
coating the integrated circuit with a second layer of a photosensitive polymer dielectric wherein the second layer overlies the first layer;
forming a second opening with a second layer edge in the second layer, wherein the second opening is larger than the IC opening and wherein the second opening is smaller than the first opening and wherein the second opening and the first opening are concentric; and
curing the second layer;
wherein the IC opening and the first opening are concentric;
wherein the IC opening is smaller than the first opening;
wherein the second layer covers the first layer edge; and
wherein the overlying layer covers the second layer edge.

15. The process of claim 14 , further comprising:
coating the integrated circuit with a third layer of a photosensitive polymer dielectric wherein the third layer overlies the first layer and the second layer and wherein the overlying layer overlies the third layer;
exposing a third opening in the third layer using a third opening photo mask, wherein the third opening is larger than the IC opening and smaller than the first opening and the second opening;
developing the third layer to form the third opening with a third layer edge;
curing the third layer;
wherein the third layer overlies the second layer edge; and
wherein the third opening and the first opening are concentric.

16. The process of claim 14 , wherein the photosensitive polymer dielectric a photosensitive polymer such as polyimide, polybenzobisoxazole (PBO), SU-8 (epoxy-based photosensitive polymer), or BCB (benzocyclobutene-based photosensitive polymer).

17. The integrated circuit of claim 14 , wherein the photosensitive polymer dielectric is a photosensitive polyimide.

Assignees

• Texas Instruments Inc

Inventors

• Han Licheng Marshal
• Serafin Michael Andrew
• Williams Byron
• Varela Sandra Rodriguez
• Pavone Salvatore

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title